u-boot.git/arch/mips/cpu/mips32, branch v2012.04

MIPS: fix endianess handling

2012-04-02T13:54:53Z

Make endianess of target CPU configurable. Use the new config option for dbau1550_el and pb1000 boards. Adapt linking of standalone applications to pass through endianess options to LD. Build tested with: - ELDK 4 mips_4KC- and mips4KCle - Sourcery CodeBench Lite 2011.03-93 With this patch all 26 MIPS boards can be compiled now in one step by running "MAKEALL -a mips". Signed-off-by: Daniel Schwierzeck

MIPS: fix inconsistency in config option for cache operation mode

2012-04-02T13:54:53Z

Commit ab2a98b11716364bc5a8c43cdfa7fee176cda1d8 missed to use the new config option in dcache_enable(). Fix this to avoid inconsistencies if someone wants to disable and enable D-caches. Signed-off-by: Daniel Schwierzeck

usb: replace wait_ms() with mdelay()

2012-03-18T23:08:16Z

Common code has a mdelay() func, so use that instead of the usb-specific wait_ms() func. This also fixes the build errors: ohci-hcd.c: In function 'submit_common_msg': /usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available ohci-hcd.c:1519:9: sorry, unimplemented: called from here /usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available ohci-hcd.c:1816:10: sorry, unimplemented: called from here /usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available ohci-hcd.c:1827:10: sorry, unimplemented: called from here /usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available ohci-hcd.c:1844:10: sorry, unimplemented: called from here /usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available ohci-hcd.c:1563:11: sorry, unimplemented: called from here /usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available ohci-hcd.c:1583:9: sorry, unimplemented: called from here make[1]: *** [ohci-hcd.o] Error 1 Signed-off-by: Mike Frysinger Acked-by: Marek Vasut

consolidate mdelay by providing a common function for all users

2011-10-21T23:16:08Z

There are several mdelay() definitions in the driver and board code. Remove them all and provide a common mdelay() in lib/time.c. Signed-off-by: Anatolij Gustschin Acked-by: Mike Frysinger

MIPS: mips32: fix wrong loop bound in flush_cache()

2011-09-03T01:43:45Z

The issue is found when calling flush_cache() with zero "size" argument. The bound of loop is miscalculated in this case and flush_cache() enters a wrong flushing loop. Signed-off-by: Yao Cheng Cc: Shinya Kuribayashi Cc: Sergei Shtylyov Cc: Mike Frysinger Signed-off-by: Shinya Kuribayashi

MIPS: make cache operation mode configurable

2011-07-31T14:26:41Z

Currently the cache operation mode is hard-coded to CONF_CM_CACHABLE_NONCOHERENT. This is not appropiate for CPUs or SOCs which operate at a different mode. This patch makes the cache operation mode configurable via board config. Signed-off-by: Daniel Schwierzeck Acked-by: Thomas Langer Signed-off-by: Shinya Kuribayashi

MIPS: rename INFINEON_EBU_BOOTCFG to CONFIG_SYS_XWAY_EBU_BOOTFG

2011-07-31T14:26:41Z

This define is a board-specific config option and should be renamed to follow the U-Boot naming convention. Additionally, add an explaining comment for this option. Signed-off-by: Daniel Schwierzeck Acked-by: Thomas Langer Signed-off-by: Shinya Kuribayashi

Timer: Remove reset_timer() for non-Nios2 arches

2011-07-26T12:53:30Z

Timer: Remove set_timer completely

2011-07-26T12:52:17Z

MIPS: Move timer code to arch/mips/cpu/$(CPU)/

2011-05-09T15:12:31Z

Current timer routines (arch/mips/lib/timer.c) are implemented assuming that MIPS32 coprocessor (CP0) resources, Counter and Compare registers in this case, are available. But this doesn't always work. We need to make sure that all MIPS-based systems don't necessarily use CP0 counter/compare registers as time keeping resources. And some MIPS variant processors might come with different hardware specs with genuine MIPS32 CP0 registers. With this change, each $(CPU)/ directory can have its own timer code. Signed-off-by: Shinya Kuribayashi