u-boot.git/arch/mips/cpu/start.S, branch v2022.07

Convert CONFIG_SKIP_LOWLEVEL_INIT et al to Kconfig

2021-08-31T21:47:49Z

This converts the following to Kconfig: CONFIG_SKIP_LOWLEVEL_INIT CONFIG_SKIP_LOWLEVEL_INIT_ONLY In order to do this, we need to introduce SPL and TPL variants of these options so that we can clearly disable these options only in SPL in some cases, and both instances in other cases. Signed-off-by: Tom Rini

mips: start.S: Add Octeon boot header compatibility

2020-11-30T17:31:56Z

Octeon has a specific boot header, when booted via SPI NOR, NAND or MMC. Here the only 2 instructions are allowed in the first few bytes of the image. And these instructions need to be one branch and a nop. This patch adds the necessary nop after the nop, to that the common MIPS image is compatible with this Octeon header. The tool to patch the Octeon boot header into the image will be send in a follow-up patch. Signed-off-by: Stefan Roese Cc: Aaron Williams Cc: Chandrakala Chavva Cc: Daniel Schwierzeck Reviewed-by: Daniel Schwierzeck

mips: Add CONFIG_MIPS_MACH_EARLY_INIT for very early mach init code

2020-07-18T12:23:25Z

This patch adds the optional call to mips_mach_early_init() to start.S at a very early stage. Its disabled per default. It can be used for very early machine / platform specific init code. Its called very early and at this stage the PC is allowed to differ from the linking address (CONFIG_TEXT_BASE) as no absolute jump has been performed until this call. It will be used by thje Octeon platform. Signed-off-by: Stefan Roese Reviewed-by: Daniel Schwierzeck

mips: sync asm/mipsregs.h with Linux 5.7

2020-07-18T12:23:25Z

Sync asm/mipsregs.h with Linux 5.7. Also replace the custom symbols EBASE_CPUNUM and EBASE_WG with the according symbols from Linux. Signed-off-by: Daniel Schwierzeck Reviewed-by: Stefan Roese Tested-by: Stefan Roese

mips: add config options for generic cache setup code

2020-07-18T12:23:25Z

Add an own Kconfig symbol for the initial disabling of caches invoked from generic start code. Also add an own Kconfig symbols for the initialization of caches invoked from generic start code. Until now both code paths could only be disabled with CONFIG_SKIP_LOWLEVEL_INIT. But this is not flexible enough for RAM boot scenarios like EJTAG or SPL payload or for machines which don't require cache initialization or which want to provide their own cache implementation. Signed-off-by: Daniel Schwierzeck Reviewed-by: Stefan Roese Tested-by: Stefan Roese

mips: refactor disabling of caches

2020-07-18T12:23:25Z

Logically this code belongs to cache_init.S. If a complex SoC needs to replace the generic cache init, mips_cache_disable() can now be called from custom start.S files. Signed-off-by: Daniel Schwierzeck Reviewed-by: Stefan Roese Tested-by: Stefan Roese

mips: start.S: remove dead code

2020-07-18T12:23:25Z

Since commit 703ec9ddf965 ("MIPS: Stop building position independent code") the relocation code was completely reworked and removed from start.S. Remove some left-overs of the old code. Signed-off-by: Daniel Schwierzeck Reviewed-by: Stefan Roese Tested-by: Stefan Roese

mips: add a option to support not reserving malloc space on initial stack

2020-04-27T18:29:33Z

The initial stack on some platforms is too small to hold a large malloc space. This patch adds a option to allow these platforms not reserving the malloc space on initial stack. These platforms should set the malloc base after DRAM is usable. Reviewed-by: Stefan Roese Signed-off-by: Weijie Gao

mips: add an option to support initialize SRAM for initial stack

2020-04-27T18:29:33Z

Currently CONFIG_MIPS_INIT_STACK_IN_SRAM assumes the memory space for the initial stack can be used directly. However on some platform the SRAM needs initialization, e.g. lock cache. This patch adds an option to allow a new function mips_sram_init() being called before setup_stack_gd. Reviewed-by: Daniel Schwierzeck Reviewed-by: Stefan Roese Signed-off-by: Weijie Gao

mips: start.S: avoid overwriting outside gd when clearing global data in stack

2020-04-27T18:29:33Z

When setting up initial stack, global data will also be put in the stack, and being cleared. The assembler instructions for clearing gd is as follows: move t0, k0 1: PTR_S zero, 0(t0) blt t0, t1, 1b PTR_ADDIU t0, PTRSIZE t0 is the start address of gd, t1 is the end address of gd (t0 + GD_SIZE). [PTR_ADDIU t0, PTRSIZE] is in the delay slot of [blt t0, t1, 1b], so it will be executed before the branch operation. However the comparison for the BLT instruction is done before executing the delay slot. This means when the last word just before k1 is cleared, the loop will continue to run once. This will clear an extra word at k1, which is outside the global data. Global data is placed at the top of the stack. If the initial stack is a SRAM or locked cache, the area outside them may be inaccessible. A write operation performed in this area may cause an exception. To solve this, [PTR_ADDIU t0, PTRSIZE] should be placed before the BLT instruction. Reviewed-by: Daniel Schwierzeck Reviewed-by: Stefan Roese Signed-off-by: Weijie Gao