u-boot.git/arch/mips/cpu, branch v2012.04

MIPS: fix endianess handling

2012-04-02T13:54:53+00:00

Make endianess of target CPU configurable. Use the new config
option for dbau1550_el and pb1000 boards.

Adapt linking of standalone applications to pass through
endianess options to LD.

Build tested with:
 - ELDK 4 mips_4KC- and mips4KCle
 - Sourcery CodeBench Lite 2011.03-93

With this patch all 26 MIPS boards can be compiled now in one step by
running "MAKEALL -a mips".

Signed-off-by: Daniel Schwierzeck

MIPS: fix inconsistency in config option for cache operation mode

2012-04-02T13:54:53+00:00

Commit ab2a98b11716364bc5a8c43cdfa7fee176cda1d8 missed to
use the new config option in dcache_enable().

Fix this to avoid inconsistencies if someone wants to disable
and enable D-caches.

Signed-off-by: Daniel Schwierzeck

usb: replace wait_ms() with mdelay()

2012-03-18T23:08:16+00:00

Common code has a mdelay() func, so use that instead of the usb-specific
wait_ms() func.  This also fixes the build errors:

ohci-hcd.c: In function 'submit_common_msg':
/usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available
ohci-hcd.c:1519:9: sorry, unimplemented: called from here
/usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available
ohci-hcd.c:1816:10: sorry, unimplemented: called from here
/usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available
ohci-hcd.c:1827:10: sorry, unimplemented: called from here
/usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available
ohci-hcd.c:1844:10: sorry, unimplemented: called from here
/usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available
ohci-hcd.c:1563:11: sorry, unimplemented: called from here
/usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available
ohci-hcd.c:1583:9: sorry, unimplemented: called from here
make[1]: *** [ohci-hcd.o] Error 1

Signed-off-by: Mike Frysinger 
Acked-by: Marek Vasut

consolidate mdelay by providing a common function for all users

2011-10-21T23:16:08+00:00

There are several mdelay() definitions in the driver and
board code. Remove them all and provide a common mdelay()
in lib/time.c.

Signed-off-by: Anatolij Gustschin 
Acked-by: Mike Frysinger

MIPS: Ingenic XBurst Jz4740 processor support

2011-10-10T13:06:12+00:00

Jz4740 is a multimedia application processor targeting for mobile
devices like e-Dictionary, eBook, portable media player (PMP) and
GPS navigator.  Jz4740 is powered by Ingenic 360 MHz XBurst CPU core
(JzRISC), in which RISC/SIMD/DSP hybrid instruction set architecture
provides high integration, high performance and low power consumption.

JzRISC incorporated in Jz4740 is the advanced and power-efficient
32-bit RISC core, compatible with MIPS32, with 16K I-Cache and 16K
D-Cache, and can operate at speeds up to 400 MHz.

On-chip modules such as LCD controller, embedded audio codec, multi-
channel SAR-ADC, AC97/I2S controller and camera I/F offer a rich
suite of peripherals for multimedia application.  NAND controller
(SLC/MLC), USB (host 1.1 and device 2.0), UART, I2C, SPI, etc. are
also available.

For more info about Ingenic XBurst Jz4740:
  http://en.ingenic.cn/eng/
  http://www.linux-mips.org/wiki/Ingenic

This patch introduces XBurst CPU support in U-Boot.  It's compatible
with MIPS32, but requires a bit different cache maintenance, timer
routines, and boot mechanism using USB boot tool, so XBurst support
can go into a separate new home, cpu/xburst/.

Signed-off-by: Xiangfu Liu 
Acked-by: Daniel 
Signed-off-by: Shinya Kuribayashi

MIPS: mips32: fix wrong loop bound in flush_cache()

2011-09-03T01:43:45+00:00

The issue is found when calling flush_cache() with zero "size" argument.
The bound of loop is miscalculated in this case and flush_cache() enters
a wrong flushing loop.

Signed-off-by: Yao Cheng 
Cc: Shinya Kuribayashi 
Cc: Sergei Shtylyov 
Cc: Mike Frysinger 
Signed-off-by: Shinya Kuribayashi

MIPS: make cache operation mode configurable

2011-07-31T14:26:41+00:00

Currently the cache operation mode is hard-coded to
CONF_CM_CACHABLE_NONCOHERENT. This is not appropiate for CPUs or SOCs
which operate at a different mode.

This patch makes the cache operation mode configurable via board config.

Signed-off-by: Daniel Schwierzeck 
Acked-by: Thomas Langer 
Signed-off-by: Shinya Kuribayashi

MIPS: rename INFINEON_EBU_BOOTCFG to CONFIG_SYS_XWAY_EBU_BOOTFG

2011-07-31T14:26:41+00:00

This define is a board-specific config option and should be
renamed to follow the U-Boot naming convention. Additionally,
add an explaining comment for this option.

Signed-off-by: Daniel Schwierzeck 
Acked-by: Thomas Langer 
Signed-off-by: Shinya Kuribayashi

Timer: Remove reset_timer() for non-Nios2 arches

2011-07-26T12:53:30+00:00

Timer: Remove set_timer completely

2011-07-26T12:52:17+00:00