u-boot.git/arch/mips/include/asm/global_data.h, branch master

mips: drop volatile qualifier from gd pointer

2025-06-13T22:57:14+00:00

Signed-off-by: Rasmus Villemoes

Restore patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"

2024-05-20T19:35:03+00:00

As part of bringing the master branch back in to next, we need to allow
for all of these changes to exist here.

Reported-by: Jonas Karlman 
Signed-off-by: Tom Rini

Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""

2024-05-19T14:16:36+00:00

When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay
Ethernet"' I failed to notice that b4 noticed it was based on next and
so took that as the base commit and merged that part of next to master.

This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing
changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35.

Reported-by: Jonas Karlman 
Signed-off-by: Tom Rini

global: Make include

2024-05-06T21:07:48+00:00

This follows the example of RISC-V where  includes
 directly as "gd" includes a reference to bd_info already
and so the first must include the second anyhow. We then remove
 from all of the places which include references to "gd"
an so have  already.

Signed-off-by: Tom Rini

global: Rework architecture global_data.h to include

2023-12-21T13:54:37+00:00

In most cases, the architecture global data currently makes use of
assorted linux types, but does not include  to provide
them. Add  instead of relying on indirect inclusion.

Reviewed-by: Simon Glass 
Signed-off-by: Tom Rini

mips: global_data.h: Add Octeon specific data to arch_global_data struct

2021-04-23T19:02:12+00:00

This will be used by the upcoming Serdes and driver code ported from
the original 2013 U-Boot code to mainline.

Signed-off-by: Stefan Roese

mips: add a mtmips-specific field to architecture-specific global data

2020-04-27T18:29:33+00:00

SoCs of mtmips can use different CPU frequencies depending on the HW/SW
configurations. For example mt7628 uses 580MHz clock if the input xtal
frequency is 40MHz, and 575MHz clock if the xtal is 25MHz. Upon cold boot
the CPU uses the xtal frequency directly.

So hardcoding the timer frequency (half of the CPU frequency) in
CONFIG_SYS_MIPS_TIMER_FREQ is not a good idea for this case.

This patch adds a mtmips-specific field timer_freq to arch_global_data.
This field will be used later in mtmips-specific get_tbclk() to provide
accurate timer frequency in different boot stage.

Reviewed-by: Stefan Roese 
Reviewed-by: Daniel Schwierzeck 
Signed-off-by: Weijie Gao

SPDX: Convert all of our single license tags to Linux Kernel style

2018-05-07T13:34:12+00:00

When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents.  There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini

MIPS: L2 cache support

2016-09-21T13:04:04+00:00

This patch adds support for initialising & maintaining L2 caches on MIPS
systems. The L2 cache configuration may be advertised through either
coprocessor 0 or the MIPS Coherence Manager depending upon the system,
and support for both is included.

If the L2 can be bypassed then we bypass it early in boot & initialise
the L1 caches first, such that we can start making use of the L1
instruction cache as early as possible. Otherwise we initialise the L2
first such that the L1s have no opportunity to generate access to the
uninitialised L2.

Signed-off-by: Paul Burton

MIPS: Probe cache line sizes once during boot

2016-09-21T13:04:04+00:00

Rather than probing the cache line sizes on every call of any cache
maintenance function, probe them once during boot & store the values in
the global data structure for later use. This will reduce the overhead
of the cache maintenance functions, which isn't a big deal yet but
becomes more important once L2 caches which may expose their properties
via coprocessor 2 or the CM are supported.

Signed-off-by: Paul Burton