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<title>u-boot.git/arch/mips/include/asm/global_data.h, branch v2024.04</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/mips/include/asm/global_data.h?h=v2024.04</id>
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<updated>2023-12-21T13:54:37Z</updated>
<entry>
<title>global: Rework architecture global_data.h to include &lt;linux/types.h&gt;</title>
<updated>2023-12-21T13:54:37Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2023-12-14T18:16:52Z</published>
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<id>urn:sha1:071cf2767f832ec89eff40a476903d4ac5240dcf</id>
<content type='text'>
In most cases, the architecture global data currently makes use of
assorted linux types, but does not include &lt;linux/types.h&gt; to provide
them. Add &lt;linux/types.h&gt; instead of relying on indirect inclusion.

Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>mips: global_data.h: Add Octeon specific data to arch_global_data struct</title>
<updated>2021-04-23T19:02:12Z</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2020-12-11T16:05:23Z</published>
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<id>urn:sha1:2d80cbfb0556eea18f0e3a10a1c0fa48282429d1</id>
<content type='text'>
This will be used by the upcoming Serdes and driver code ported from
the original 2013 U-Boot code to mainline.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>mips: add a mtmips-specific field to architecture-specific global data</title>
<updated>2020-04-27T18:29:33Z</updated>
<author>
<name>Weijie Gao</name>
<email>weijie.gao@mediatek.com</email>
</author>
<published>2020-04-21T07:28:32Z</published>
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<id>urn:sha1:a60c1e6d6b682e432e4d6293da5566e0ddc7d3b8</id>
<content type='text'>
SoCs of mtmips can use different CPU frequencies depending on the HW/SW
configurations. For example mt7628 uses 580MHz clock if the input xtal
frequency is 40MHz, and 575MHz clock if the xtal is 25MHz. Upon cold boot
the CPU uses the xtal frequency directly.

So hardcoding the timer frequency (half of the CPU frequency) in
CONFIG_SYS_MIPS_TIMER_FREQ is not a good idea for this case.

This patch adds a mtmips-specific field timer_freq to arch_global_data.
This field will be used later in mtmips-specific get_tbclk() to provide
accurate timer frequency in different boot stage.

Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
Reviewed-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
Signed-off-by: Weijie Gao &lt;weijie.gao@mediatek.com&gt;
</content>
</entry>
<entry>
<title>SPDX: Convert all of our single license tags to Linux Kernel style</title>
<updated>2018-05-07T13:34:12Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2018-05-06T21:58:06Z</published>
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<id>urn:sha1:83d290c56fab2d38cd1ab4c4cc7099559c1d5046</id>
<content type='text'>
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents.  There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>MIPS: L2 cache support</title>
<updated>2016-09-21T13:04:04Z</updated>
<author>
<name>Paul Burton</name>
<email>paul.burton@imgtec.com</email>
</author>
<published>2016-09-21T10:18:54Z</published>
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<id>urn:sha1:4baa0ab67d504f3b4318f999631e3f83d0c52c4a</id>
<content type='text'>
This patch adds support for initialising &amp; maintaining L2 caches on MIPS
systems. The L2 cache configuration may be advertised through either
coprocessor 0 or the MIPS Coherence Manager depending upon the system,
and support for both is included.

If the L2 can be bypassed then we bypass it early in boot &amp; initialise
the L1 caches first, such that we can start making use of the L1
instruction cache as early as possible. Otherwise we initialise the L2
first such that the L1s have no opportunity to generate access to the
uninitialised L2.

Signed-off-by: Paul Burton &lt;paul.burton@imgtec.com&gt;
</content>
</entry>
<entry>
<title>MIPS: Probe cache line sizes once during boot</title>
<updated>2016-09-21T13:04:04Z</updated>
<author>
<name>Paul Burton</name>
<email>paul.burton@imgtec.com</email>
</author>
<published>2016-09-21T10:18:48Z</published>
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<id>urn:sha1:8cb4817d0f076605c5126f0925f6c7fdb0461bf6</id>
<content type='text'>
Rather than probing the cache line sizes on every call of any cache
maintenance function, probe them once during boot &amp; store the values in
the global data structure for later use. This will reduce the overhead
of the cache maintenance functions, which isn't a big deal yet but
becomes more important once L2 caches which may expose their properties
via coprocessor 2 or the CM are supported.

Signed-off-by: Paul Burton &lt;paul.burton@imgtec.com&gt;
</content>
</entry>
<entry>
<title>mips: Drop JZ4740 remnants</title>
<updated>2016-05-25T23:34:14Z</updated>
<author>
<name>Marek Vasut</name>
<email>marex@denx.de</email>
</author>
<published>2016-05-25T00:17:07Z</published>
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<id>urn:sha1:1ad3a6fb5b9eb8444281c3975de6c6b7e1549c53</id>
<content type='text'>
Remove the remnants of JZ4740 support.

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
Cc: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
Cc: Paul Burton &lt;paul.burton@imgtec.com&gt;
</content>
</entry>
<entry>
<title>mips: add base support for QCA/Atheros ath79 SOCs</title>
<updated>2016-05-20T23:25:50Z</updated>
<author>
<name>Wills Wang</name>
<email>wills.wang@live.com</email>
</author>
<published>2016-03-16T08:59:52Z</published>
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<id>urn:sha1:1d3d0f1f1cd8bac8ea0135c92a2bcd5020abfb1d</id>
<content type='text'>
This patch add some common code for QCA/Atheros ath79 SOCs such as
DDR tuning, chip reset and CPU detection.

Signed-off-by: Wills Wang &lt;wills.wang@live.com&gt;
</content>
</entry>
<entry>
<title>MIPS: Support dynamic I/O port base address</title>
<updated>2016-02-01T21:13:25Z</updated>
<author>
<name>Paul Burton</name>
<email>paul.burton@imgtec.com</email>
</author>
<published>2016-01-29T13:54:52Z</published>
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<id>urn:sha1:05e342554e51767830d7e60f2dab09192fd2a0e1</id>
<content type='text'>
The existing mips_io_port_base variable isn't suitable for use early
during boot since it will be stored in the .data section which may not
be writable pre-relocation. Fix this by moving the I/O port base address
into struct arch_global_data. In order to avoid adding this field for
all targets, make this dependant upon a new Kconfig entry
CONFIG_DYNAMIC_IO_PORT_BASE. Malta is the only board which sets a
non-zero I/O port base, so select this option only for Malta.

Signed-off-by: Paul Burton &lt;paul.burton@imgtec.com&gt;
</content>
</entry>
<entry>
<title>Add GPL-2.0+ SPDX-License-Identifier to source files</title>
<updated>2013-07-24T13:44:38Z</updated>
<author>
<name>Wolfgang Denk</name>
<email>wd@denx.de</email>
</author>
<published>2013-07-08T07:37:19Z</published>
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<id>urn:sha1:1a4596601fd395f3afb8f82f3f840c5e00bdd57a</id>
<content type='text'>
Signed-off-by: Wolfgang Denk &lt;wd@denx.de&gt;
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini &lt;trini@ti.com&gt;
</content>
</entry>
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