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<title>u-boot.git/arch/mips/include, branch v2016.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>mips: Use the generic bitops headers</title>
<updated>2015-11-05T15:52:26+00:00</updated>
<author>
<name>Fabio Estevam</name>
<email>fabio.estevam@freescale.com</email>
</author>
<published>2015-11-05T14:43:35+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=b810aa1dd1b2c7facf47ca607cd780ec7976fd16'/>
<id>b810aa1dd1b2c7facf47ca607cd780ec7976fd16</id>
<content type='text'>
The generic bitops headers are required when calling logarithmic
functions, such as ilog2().

Signed-off-by: Fabio Estevam &lt;fabio.estevam@freescale.com&gt;
Reviewed-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
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<pre>
The generic bitops headers are required when calling logarithmic
functions, such as ilog2().

Signed-off-by: Fabio Estevam &lt;fabio.estevam@freescale.com&gt;
Reviewed-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>mips: Use unsigned int when reading c0 registers</title>
<updated>2015-08-21T13:22:41+00:00</updated>
<author>
<name>Chris Packham</name>
<email>judge.packham@gmail.com</email>
</author>
<published>2015-07-14T10:54:41+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=73a4152b2579c86f4401e0984c70eed7dd8cedfa'/>
<id>73a4152b2579c86f4401e0984c70eed7dd8cedfa</id>
<content type='text'>
In commit a18a477 (MIPS: use common code from lib/time.c) MIPS platforms
started using common the common timer functions which are based around
the fact that many platforms have a 32-bit free running counter register
that can be used see commit 8dfafdd (Introduce common timer functions).

Even MIPS64 has such a 32-bit register (some have an additional 64-bit free
running counter, but that's something for another time).

The problem is that in __read_32bit_c0_register() we read the value from
this register into an _signed_ int and as it's returned up the call
chain to timer_read_counter() it gets assigned to an unsigned long. On a
32-bit system there is no problem. On a 64-bit system odd things happen,
sign extension seems to kick in and all of a sudden if the counter
register happens to have the MSb (i.e. the sign bit) set the negative
int gets sign extended into a very large unsigned long value. This in
turn throws out things from get_ticks() up.

Update __read_32bit_c0_register() and __read_32bit_c0_ctrl_register() to
use "unsigned int res;" instead of "int res;". There seems to be little
reason to treat these register values as signed. They are either
counters (which by definition are unsigned) or are made up of various
bit fields to be interpreted as per the CPU datasheet.

Reported-by: Sachin Surendran &lt;sachin.surendran@alliedtelesis.co.nz&gt;
Signed-off-by: Chris Packham &lt;judge.packham@gmail.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
In commit a18a477 (MIPS: use common code from lib/time.c) MIPS platforms
started using common the common timer functions which are based around
the fact that many platforms have a 32-bit free running counter register
that can be used see commit 8dfafdd (Introduce common timer functions).

Even MIPS64 has such a 32-bit register (some have an additional 64-bit free
running counter, but that's something for another time).

The problem is that in __read_32bit_c0_register() we read the value from
this register into an _signed_ int and as it's returned up the call
chain to timer_read_counter() it gets assigned to an unsigned long. On a
32-bit system there is no problem. On a 64-bit system odd things happen,
sign extension seems to kick in and all of a sudden if the counter
register happens to have the MSb (i.e. the sign bit) set the negative
int gets sign extended into a very large unsigned long value. This in
turn throws out things from get_ticks() up.

Update __read_32bit_c0_register() and __read_32bit_c0_ctrl_register() to
use "unsigned int res;" instead of "int res;". There seems to be little
reason to treat these register values as signed. They are either
counters (which by definition are unsigned) or are made up of various
bit fields to be interpreted as per the CPU datasheet.

Reported-by: Sachin Surendran &lt;sachin.surendran@alliedtelesis.co.nz&gt;
Signed-off-by: Chris Packham &lt;judge.packham@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>MIPS: change 'extern inline' to 'static inline'</title>
<updated>2015-07-02T09:29:33+00:00</updated>
<author>
<name>Daniel Schwierzeck</name>
<email>daniel.schwierzeck@gmail.com</email>
</author>
<published>2015-07-01T14:36:43+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=b11c5d1dc29e81326d1215011d19377737082aeb'/>
<id>b11c5d1dc29e81326d1215011d19377737082aeb</id>
<content type='text'>
The kernel changed it a long time ago. Also this is now broken
on gcc-5.x.

Reported-by: Andy Kennedy &lt;andy.kennedy@adtran.com&gt;
Signed-off-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
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<pre>
The kernel changed it a long time ago. Also this is now broken
on gcc-5.x.

Reported-by: Andy Kennedy &lt;andy.kennedy@adtran.com&gt;
Signed-off-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>MIPS: fix missing semicolon in cacheops.h</title>
<updated>2015-07-02T09:29:33+00:00</updated>
<author>
<name>Tony Wu</name>
<email>tung7970@gmail.com</email>
</author>
<published>2015-05-30T07:02:39+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=49bbdae318e31758cab7ed15aa29abd8ad18de13'/>
<id>49bbdae318e31758cab7ed15aa29abd8ad18de13</id>
<content type='text'>
Fix missing semicolon in cacheops.h introduced in commit
2b8bcc5a2 (MIPS: avoid .set ISA for cache operations)

Signed-off-by: Tony Wu &lt;tung7970@gmail.com&gt;
Cc: Paul Burton &lt;paul.burton@imgtec.com&gt;
</content>
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<pre>
Fix missing semicolon in cacheops.h introduced in commit
2b8bcc5a2 (MIPS: avoid .set ISA for cache operations)

Signed-off-by: Tony Wu &lt;tung7970@gmail.com&gt;
Cc: Paul Burton &lt;paul.burton@imgtec.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>malta: IDE support</title>
<updated>2015-01-29T12:11:02+00:00</updated>
<author>
<name>Paul Burton</name>
<email>paul.burton@imgtec.com</email>
</author>
<published>2015-01-29T10:38:20+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ba21a453a58fc02b890f4064b293b1cb09fe7484'/>
<id>ba21a453a58fc02b890f4064b293b1cb09fe7484</id>
<content type='text'>
This patch adds IDE support to the MIPS Malta board. The IDE controller
is enabled after probing the PCI bus and otherwise just makes use of
U-boot generic IDE support.

Signed-off-by: Paul Burton &lt;paul.burton@imgtec.com&gt;
Cc: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This patch adds IDE support to the MIPS Malta board. The IDE controller
is enabled after probing the PCI bus and otherwise just makes use of
U-boot generic IDE support.

Signed-off-by: Paul Burton &lt;paul.burton@imgtec.com&gt;
Cc: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>MIPS: avoid .set ISA for cache operations</title>
<updated>2015-01-29T11:55:00+00:00</updated>
<author>
<name>Paul Burton</name>
<email>paul.burton@imgtec.com</email>
</author>
<published>2015-01-29T01:27:56+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=2b8bcc5a2fca54648ece966902b8230de971b609'/>
<id>2b8bcc5a2fca54648ece966902b8230de971b609</id>
<content type='text'>
As a step towards unifying the cache maintenance code for mips32 &amp;
mips64 CPUs, stop using ".set &lt;ISA&gt;" directives in the more developed
mips32 version of the code. Instead, when present make use of the GCC
builtin for emitting a cache instruction. When not present, simply don't
bother with the .set directives since U-boot always builds with
-march=mips32 or higher anyway.

Signed-off-by: Paul Burton &lt;paul.burton@imgtec.com&gt;
Cc: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
</content>
<content type='xhtml'>
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<pre>
As a step towards unifying the cache maintenance code for mips32 &amp;
mips64 CPUs, stop using ".set &lt;ISA&gt;" directives in the more developed
mips32 version of the code. Instead, when present make use of the GCC
builtin for emitting a cache instruction. When not present, simply don't
bother with the .set directives since U-boot always builds with
-march=mips32 or higher anyway.

Signed-off-by: Paul Burton &lt;paul.burton@imgtec.com&gt;
Cc: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>MIPS: add support for pre-relocation malloc</title>
<updated>2015-01-21T13:07:23+00:00</updated>
<author>
<name>Daniel Schwierzeck</name>
<email>daniel.schwierzeck@gmail.com</email>
</author>
<published>2015-01-18T21:18:39+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=e520023882c7187a7cbaecfea0726ea158440aef'/>
<id>e520023882c7187a7cbaecfea0726ea158440aef</id>
<content type='text'>
Implement MIPS specific setup of the gd_t structure to support
pre-relocation malloc. If CONFIG_SYS_MALLOC_F_LEN is specified,
a memory area will be reserved after the initial stack area and
the gd-&gt;malloc_base pointer will be initialized.

After this patch the new driver model can be used on MIPS.

Signed-off-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
</content>
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<pre>
Implement MIPS specific setup of the gd_t structure to support
pre-relocation malloc. If CONFIG_SYS_MALLOC_F_LEN is specified,
a memory area will be reserved after the initial stack area and
the gd-&gt;malloc_base pointer will be initialized.

After this patch the new driver model can be used on MIPS.

Signed-off-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Replace &lt;compiler.h&gt; with &lt;linux/compiler.h&gt;</title>
<updated>2014-12-08T14:35:46+00:00</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.m@jp.panasonic.com</email>
</author>
<published>2014-11-26T07:00:58+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=afc366f01bea2361bc08b1a7b51e0cef81d66173'/>
<id>afc366f01bea2361bc08b1a7b51e0cef81d66173</id>
<content type='text'>
Including &lt;linux/compiler.h&gt; is enough for general use.

Signed-off-by: Masahiro Yamada &lt;yamada.m@jp.panasonic.com&gt;
</content>
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<pre>
Including &lt;linux/compiler.h&gt; is enough for general use.

Signed-off-by: Masahiro Yamada &lt;yamada.m@jp.panasonic.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>common/board_f: Initialized global data for generic board</title>
<updated>2014-05-12T19:20:05+00:00</updated>
<author>
<name>York Sun</name>
<email>yorksun@freescale.com</email>
</author>
<published>2014-05-03T00:28:04+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=2a1680e30e3fa8257b60cb9dbd7add32539ac470'/>
<id>2a1680e30e3fa8257b60cb9dbd7add32539ac470</id>
<content type='text'>
Some platforms (tested on mpc85xx, mpc86xx) use global data before calling
function baord_inti_f(). The data should not be cleared later. Any arch
which uses global data in generic board board_init_f() should define
CONFIG_SYS_GENERIC_GLOBAL_DATA.

Signed-off-by: York Sun &lt;yorksun@freescale.com&gt;
CC: Scott Wood &lt;scottwood@freescale.com&gt;
CC: Simon Glass &lt;sjg@chromium.org&gt;
CC: Albert ARIBAUD &lt;albert.u.boot@aribaud.net&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
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<pre>
Some platforms (tested on mpc85xx, mpc86xx) use global data before calling
function baord_inti_f(). The data should not be cleared later. Any arch
which uses global data in generic board board_init_f() should define
CONFIG_SYS_GENERIC_GLOBAL_DATA.

Signed-off-by: York Sun &lt;yorksun@freescale.com&gt;
CC: Scott Wood &lt;scottwood@freescale.com&gt;
CC: Simon Glass &lt;sjg@chromium.org&gt;
CC: Albert ARIBAUD &lt;albert.u.boot@aribaud.net&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>bd_info: remove bi_barudrate member from struct bd_info</title>
<updated>2014-05-12T19:19:45+00:00</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.m@jp.panasonic.com</email>
</author>
<published>2014-04-04T11:09:58+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=8e2615752ee6d5daf8ce2e1e599a0512750f24b9'/>
<id>8e2615752ee6d5daf8ce2e1e599a0512750f24b9</id>
<content type='text'>
gd-&gt;bd-&gt;bi_baudrate is a copy of gd-&gt;baudrate.

Since baudrate is a common feature for all architectures,
keep gd-&gt;baudrate only.

It is true that bi_baudrate was passed to the kernel in that structure
but it was a long time ago.

Signed-off-by: Masahiro Yamada &lt;yamada.m@jp.panasonic.com&gt;
Cc: Tom Rini &lt;trini@ti.com&gt;
Cc: Simon Glass &lt;sjg@chromium.org&gt;
Cc: Wolfgang Denk &lt;wd@denx.de&gt;
Cc: Heiko Schocher &lt;hs@denx.de&gt;
Acked-by: Michal Simek &lt;monstr@monstr.eu&gt; (For microblaze)
</content>
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<pre>
gd-&gt;bd-&gt;bi_baudrate is a copy of gd-&gt;baudrate.

Since baudrate is a common feature for all architectures,
keep gd-&gt;baudrate only.

It is true that bi_baudrate was passed to the kernel in that structure
but it was a long time ago.

Signed-off-by: Masahiro Yamada &lt;yamada.m@jp.panasonic.com&gt;
Cc: Tom Rini &lt;trini@ti.com&gt;
Cc: Simon Glass &lt;sjg@chromium.org&gt;
Cc: Wolfgang Denk &lt;wd@denx.de&gt;
Cc: Heiko Schocher &lt;hs@denx.de&gt;
Acked-by: Michal Simek &lt;monstr@monstr.eu&gt; (For microblaze)
</pre>
</div>
</content>
</entry>
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