u-boot.git/arch/mips/lib/cache.c, branch v2016.05

mips: cache: Bulletproof the code against cornercases

2016-02-01T21:13:24+00:00

This patch makes sure that the flush/invalidate_dcache_range() functions
can handle corner-case calls like this -- invalidate_dcache_range(0, 0, 0);
This call is valid and is happily produced by USB EHCI code for example.
The expected behavior of the cache function(s) in this case is that they
will do no operation, since the size is zero.

The current implementation though has a problem where such invocation will
result in a hard CPU hang. This is because under such conditions, where the
start_addr = 0 and stop = 0, the addr = 0 and aend = 0xffffffe0 . The loop
will then try to iterate over the entire address space, which in itself is
wrong. But iterating over the entire address space might also hit some odd
address which will cause bus hang. The later happens on the Atheros MIPS.

Signed-off-by: Marek Vasut 
Cc: Daniel Schwierzeck 
Cc: Hans de Goede

MIPS: sync processor and register definitions with linux-4.4

2016-01-16T20:06:46+00:00

Update definitions for processor, registers as well as assemby
macros.

Signed-off-by: Daniel Schwierzeck

MIPS: unify cache maintenance functions

2015-01-29T11:55:00+00:00

Move the more developed mips32 version of the cache maintenance
functions to a common arch/mips/lib/cache.c, in order to reduce
duplication between mips32 & mips64.

Signed-off-by: Paul Burton 
Cc: Daniel Schwierzeck