u-boot.git/arch/mips/lib/cache_init.S, branch v2016.05

MIPS: sync processor and register definitions with linux-4.4

2016-01-16T20:06:46+00:00

Update definitions for processor, registers as well as assemby
macros.

Signed-off-by: Daniel Schwierzeck

MIPS: clear TagLo select 2 during cache init

2015-01-29T11:55:01+00:00

Current MIPS cores from Imagination Technologies use TagLo select 2 for
the data cache. The architecture requires that it is safe for software
to write to this register even if it isn't present, so take the trivial
option of clearing both selects 0 & 2.

Signed-off-by: Paul Burton 
Cc: Daniel Schwierzeck

MIPS: allow systems to skip loads during cache init

2015-01-29T11:55:01+00:00

Current MIPS systems do not require that loads be performed to force the
parity of cache lines, a simple invalidate by clearing the tag for each
line will suffice. Thus this patch makes the loads & subsequent second
invalidation conditional upon the CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
option, and defines that for existing mips32 targets. Exceptions are
malta where this is known to be unnecessary, and qemu-mips where caches
are not implemented.

Signed-off-by: Paul Burton 
Cc: Daniel Schwierzeck

MIPS: inline mips_init_[id]cache functions

2015-01-29T11:55:01+00:00

The mips_init_[id]cache functions are small & only called once from a
single callsite. Inlining them allows mips_cache_reset to avoid having
to bother moving arguments around & leaves it a leaf function which is
thus able to simply keep the return address live in the ra register
throughout, simplifying the code.

Signed-off-by: Paul Burton 
Cc: Daniel Schwierzeck

MIPS: refactor cache loops to a macro

2015-01-29T11:55:01+00:00

Reduce duplication by performing loops through cache tags using an
assembler macro.

Signed-off-by: Paul Burton 
Cc: Daniel Schwierzeck

MIPS: refactor L1 cache config reads to a macro

2015-01-29T11:55:01+00:00

Reduce duplication between reading the configuration of the L1 dcache &
icache by performing both using a macro which calculates the appropriate
line & cache sizes from the coprocessor 0 Config1 register.

Signed-off-by: Paul Burton 
Cc: Daniel Schwierzeck

MIPS: unify cache initialization code

2015-01-29T11:55:01+00:00

The mips32 & mips64 cache initialization code differs only in that the
mips32 code supports reading the cache size from coprocessor 0 registers
at runtime. Move the more developed mips32 version to a common
arch/mips/lib/cache_init.S & remove the now-redundant mips64 version in
order to reduce duplication. The temporary registers used are shuffled
slightly in order to work for both mips32 & mips64 builds. The RA
register is defined differently to suit mips32 & mips64, but will be
removed by a later commit in the series after further cleanup.

Signed-off-by: Paul Burton 
Cc: Daniel Schwierzeck