u-boot.git/arch/mips/lib, branch v2016.05

MIPS: bootm: Add fixup of '/memory' node.

2016-04-19T11:21:48+00:00

MIPS arch do not update 'reg' property of /memory node.
As a result Linux bootup will not work unless board.dts
file contains right /memory offset-size information or
board implements required memory fixup.
Fixing by renaming (unused) _arch_fixup_memory_node_ to
_arch_fixup_fdt_ in arch/mips/lib/bootm.c inline with ARM arch.

Signed-off-by: Purna Chandra Mandal 
Cc: Daniel Schwierzeck

MIPS: Support dynamic I/O port base address

2016-02-01T21:13:25+00:00

The existing mips_io_port_base variable isn't suitable for use early
during boot since it will be stored in the .data section which may not
be writable pre-relocation. Fix this by moving the I/O port base address
into struct arch_global_data. In order to avoid adding this field for
all targets, make this dependant upon a new Kconfig entry
CONFIG_DYNAMIC_IO_PORT_BASE. Malta is the only board which sets a
non-zero I/O port base, so select this option only for Malta.

Signed-off-by: Paul Burton

mips: cache: Bulletproof the code against cornercases

2016-02-01T21:13:24+00:00

This patch makes sure that the flush/invalidate_dcache_range() functions
can handle corner-case calls like this -- invalidate_dcache_range(0, 0, 0);
This call is valid and is happily produced by USB EHCI code for example.
The expected behavior of the cache function(s) in this case is that they
will do no operation, since the size is zero.

The current implementation though has a problem where such invocation will
result in a hard CPU hang. This is because under such conditions, where the
start_addr = 0 and stop = 0, the addr = 0 and aend = 0xffffffe0 . The loop
will then try to iterate over the entire address space, which in itself is
wrong. But iterating over the entire address space might also hit some odd
address which will cause bus hang. The later happens on the Atheros MIPS.

Signed-off-by: Marek Vasut 
Cc: Daniel Schwierzeck 
Cc: Hans de Goede

MIPS: sync processor and register definitions with linux-4.4

2016-01-16T20:06:46+00:00

Update definitions for processor, registers as well as assemby
macros.

Signed-off-by: Daniel Schwierzeck

MIPS: bootm: use CONFIG_IS_ENABLED() everywhere

2015-11-06T12:27:28+00:00

Signed-off-by: Daniel Schwierzeck 
Reviewed-by: Tom Rini

MIPS: bootm: rework and fix broken bootm code

2015-11-06T12:27:28+00:00

The move to 'generic board' as well as changes in the generic
bootm code broke the boot of FIT uImage's. Especially uImage's
with additional initramfs images or FDT's do not work anymore.

Refactor the bootm code to work again with the generic bootm code.

Always relocate ramdisk and FDT in step 'bootm prep' because the
generic bootm code does this only for legacy uImage's.

Move the step 'bootm cmdline' to 'bootm prep' because the Linux
kernel parameters rd_start and rd_size have to be initialized after
the relocation of the ramdisk.

Furthermore support the step 'bootm fake'.

Signed-off-by: Daniel Schwierzeck 
Reviewed-by: Tom Rini 
Reviewed-by: Simon Glass

MIPS: fix syntax for fdt_chosen/initrd.

2015-08-21T13:22:41+00:00

The syntax for the fdt_chosen/initrd
functions seem to deprecated in usage
from MIPS bootm implementation.

Third parameter is no more used in these api's
Refer to : include/fdt_support.h

Signed-off-by: Govindraj Raja

MIPS: implement device-tree handover to Linux kernel

2015-04-24T10:15:34+00:00

Add device-tree handover to Linux kernel conforming with MIPS UHI [1].
Register $a0 will be set to the reserved value -2. The address of
the device-tree blob will be stored as KSEG0 address in $a1. $a2 and
$a3 are set to zero.

[1] http://prplfoundation.org/wiki/MIPS_documentation

Signed-off-by: Daniel Schwierzeck

MIPS: clear TagLo select 2 during cache init

2015-01-29T11:55:01+00:00

Current MIPS cores from Imagination Technologies use TagLo select 2 for
the data cache. The architecture requires that it is safe for software
to write to this register even if it isn't present, so take the trivial
option of clearing both selects 0 & 2.

Signed-off-by: Paul Burton 
Cc: Daniel Schwierzeck

MIPS: allow systems to skip loads during cache init

2015-01-29T11:55:01+00:00

Current MIPS systems do not require that loads be performed to force the
parity of cache lines, a simple invalidate by clearing the tag for each
line will suffice. Thus this patch makes the loads & subsequent second
invalidation conditional upon the CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
option, and defines that for existing mips32 targets. Exceptions are
malta where this is known to be unnecessary, and qemu-mips where caches
are not implemented.

Signed-off-by: Paul Burton 
Cc: Daniel Schwierzeck