u-boot.git/arch/mips/lib, branch v2016.11

MIPS: Ensure cache ops complete in mips_cache_reset

2016-09-21T13:04:04Z

Ensure that cache operations complete before returning from mips_cache_reset by placing a completion barrier (sync instruction) before the return. Without this there is no guarantee that the cache ops will complete before any subsequent memory accesses, since they are indexed cache ops & thus not implicitly ordered with memory accesses. Signed-off-by: Paul Burton

MIPS: Clear hazard between TagLo writes & cache ops

2016-09-21T13:04:04Z

Writing to the coprocessor 0 TagLo registers introduces an execution hazard in that we need that write to complete before any cache instructions execute. Ensure that hazard is cleared by inserting an ehb instruction between the TagLo writes & cache op loop. Signed-off-by: Paul Burton

MIPS: Join the coherent domain when a CM is present

2016-09-21T13:04:04Z

MIPS Linux expects the bootloader to leave the boot CPU a member of the coherent domain when running on a system with a CM, and we will need to do so if we wish to make use of IOCUs to have cache-coherent DMA in U-Boot (and on some systems there is no choice in that matter). When a CM is present, join the coherent domain after completing cache initialisation. Signed-off-by: Paul Burton

MIPS: L2 cache support

2016-09-21T13:04:04Z

This patch adds support for initialising & maintaining L2 caches on MIPS systems. The L2 cache configuration may be advertised through either coprocessor 0 or the MIPS Coherence Manager depending upon the system, and support for both is included. If the L2 can be bypassed then we bypass it early in boot & initialise the L1 caches first, such that we can start making use of the L1 instruction cache as early as possible. Otherwise we initialise the L2 first such that the L1s have no opportunity to generate access to the uninitialised L2. Signed-off-by: Paul Burton

MIPS: Define register names for cache init

2016-09-21T13:04:04Z

Define names for registers holding cache sizes throughout mips_cache_reset, in order to make the code easier to read & allow for changing register assignments more easily. Signed-off-by: Paul Burton

MIPS: Enable use of the instruction cache earlier

2016-09-21T13:04:04Z

Enable use of the instruction cache immediately after it has been initialised. This will only take effect if U-Boot was linked to run from kseg0 rather than kseg1, but when this is the case the data cache initialisation code will run cached & thus significantly faster. Signed-off-by: Paul Burton

MIPS: Probe cache line sizes once during boot

2016-09-21T13:04:04Z

Rather than probing the cache line sizes on every call of any cache maintenance function, probe them once during boot & store the values in the global data structure for later use. This will reduce the overhead of the cache maintenance functions, which isn't a big deal yet but becomes more important once L2 caches which may expose their properties via coprocessor 2 or the CM are supported. Signed-off-by: Paul Burton

libfdt: Introduce new ARCH_FIXUP_FDT option

2016-08-01T01:37:08Z

Add new Kconfig option to disable arch_fixup_fdt() calls for cases where U-Boot shouldn't update memory setup in DTB file. One example of usage of this option is to boot OS with different memory setup than U-Boot use. Signed-off-by: Michal Simek Acked-by: Simon Glass

MIPS: Fix invalidate_dcache_range to operate on L1 Dcache

2016-06-10T10:27:29Z

Commit fb64cda57998 ("MIPS: Abstract cache op loops with a macro") accidentally modified invalidate_dcache_range to operate on the L1 Icache instead of the Dcache. Fix the cache op used to operate on the Dcache. Signed-off-by: Paul Burton Fixes: fb64cda57998 ("MIPS: Abstract cache op loops with a macro")

MIPS: Abstract cache op loops with a macro

2016-05-31T07:44:24Z

The various cache maintenance routines perform a number of loops over cache lines. Rather than duplicate the code for performing such loops, abstract it out into a new cache_loop macro which performs an arbitrary number of cache ops on a range of addresses. This reduces duplication in the existing L1 cache maintenance code & will allow for not adding further duplication when introducing L2 cache support. Signed-off-by: Paul Burton