u-boot.git/arch/mips/lib, branch v2020.10

mips: sync asm/mipsregs.h with Linux 5.7

2020-07-18T12:23:25+00:00

Sync asm/mipsregs.h with Linux 5.7. Also replace the custom
symbols EBASE_CPUNUM and EBASE_WG with the according symbols
from Linux.

Signed-off-by: Daniel Schwierzeck 
Reviewed-by: Stefan Roese 
Tested-by: Stefan Roese

mips: remove deprecated UNCACHED_SDRAM() macro

2020-07-18T12:23:25+00:00

This macro only served as a wrapper for CKSEG1ADDR() with an
exception for CONFIG_TB0229. CONFIG_TB0229 doesn't exist, thus
use CKSEG1ADDR() directly.

This also prepares for an upcoming asm header sync with Linux.

Signed-off-by: Daniel Schwierzeck 
Reviewed-by: Stefan Roese 
Tested-by: Stefan Roese

mips: refactor disabling of caches

2020-07-18T12:23:25+00:00

Logically this code belongs to cache_init.S.

If a complex SoC needs to replace the generic cache init,
mips_cache_disable() can now be called from custom start.S files.

Signed-off-by: Daniel Schwierzeck 
Reviewed-by: Stefan Roese 
Tested-by: Stefan Roese

mips: add KSEG1 wrapper for change_k0_cca

2020-07-18T12:23:25+00:00

change_k0_cca() is called multiple times. Move the code for
changing to KSEG1 to a macro to avoid code duplication.

Also fix missing change to KSEG1 when changing to CONF_CM_CACHABLE_COW.

Signed-off-by: Daniel Schwierzeck 
Reviewed-by: Stefan Roese 
Tested-by: Stefan Roese

mips: cache: Make invalidate_dcache_range() weak to enable overwrite

2020-07-18T12:23:25+00:00

This patch adds __weak to invalidate_dcache_range() in lib/cache.c. This
makes it possible to overwrite this function by a platforms specific
version, which will be done for Octeon.

Signed-off-by: Stefan Roese

mips: cache: Make flush_cache() weak to enable overwrite

2020-07-18T12:23:25+00:00

This patch adds __weak to flush_cache() in lib/cache.c. This makes it
possible to overwrite this function by a platforms specific version,
like done with the Octeon base port.

Signed-off-by: Stefan Roese

mips: cache: Allow using CONFIG_MIPS_L2_CACHE without CONFIG_MIPS_CM

2020-07-18T12:23:25+00:00

This patch enables the usage of CONFIG_MIPS_L2_CACHE without
CONFIG_MIPS_CM, which is what is needed for the newly added Octeon
platform.

Signed-off-by: Stefan Roese

mips: reloc: Change R_MIPS_NONE to catch pre-reloc BSS usage

2020-07-18T12:23:25+00:00

This patch changes the R_MIPS_NONE define from 0 to a magic value. This
makes it possible to better detect any forbidden pre-relocation usage
of BSS variables, as they are often zero'ed and then relocation is
stopped too early.

Additionally the error message is improved to also print the faulting
address. This helps finding the root-cause for this breakage by
comparing this address with the values in System.map.

This patch helps a lot when working on pre-relocation code, like the
Octeon DDR init code, where such variables have hit me multiple times
now.

Signed-off-by: Stefan Roese 
Cc: Daniel Schwierzeck 
Cc: Aaron Williams 
Cc: Chandrakala Chavva

mips: traps: Set WG bit in EBase register on Octeon

2020-07-18T12:23:25+00:00

WG (bit 11) needs to be set on Octeon to enable writing bits 63:30 of
the exception base register.

Signed-off-by: Stefan Roese

common: Drop linux/bitops.h from common header

2020-05-19T01:19:23+00:00

Move this uncommon header out of the common header.

Signed-off-by: Simon Glass