u-boot.git/arch/mips/mach-octeon/cache.c, branch master Unnamed repository; edit this file 'description' to name the repository. mips: octeon: cache.c: Flush all pending writes in flush_dcache_range() 2020-10-07T18:25:57+00:00 Stefan Roese sr@denx.de 2020-08-24T11:04:41+00:00 399b867fac244c4506f0a9365e7d53bfe74e66b4 As noticed while working on the USB xHCI support, Octeon needs to flush all pending writes so that the values are present in the memory. Add this "syncw" instruction (twice) to flush_dcache_range(). Signed-off-by: Stefan Roese <sr@denx.de> 
As noticed while working on the USB xHCI support, Octeon needs to flush
all pending writes so that the values are present in the memory. Add
this "syncw" instruction (twice) to flush_dcache_range().

Signed-off-by: Stefan Roese <sr@denx.de>
mips: octeon: Initial minimal support for the Marvell Octeon SoC 2020-07-18T13:47:50+00:00 Aaron Williams awilliams@marvell.com 2020-06-30T10:08:56+00:00 0dc4ab9c43ff6a235b4c0c5295a1a9747ea684c9 This patch adds very basic support for the Octeon III SoCs. Only CFI parallel NOR flash and UART is supported for now. Please note that the basic Octeon port does not include the DDR3/4 initialization yet. This will be added in some follow-up patches later. To still use U-Boot on with this port, the L2 cache (4MiB on Octeon III CN73xx) is used as RAM. This way, U-Boot can boot to the prompt on such boards. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> 
This patch adds very basic support for the Octeon III SoCs. Only
CFI parallel NOR flash and UART is supported for now.

Please note that the basic Octeon port does not include the DDR3/4
initialization yet. This will be added in some follow-up patches
later. To still use U-Boot on with this port, the L2 cache (4MiB on
Octeon III CN73xx) is used as RAM. This way, U-Boot can boot to the
prompt on such boards.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>