u-boot.git/arch/mips, branch v2011.09

MIPS: mips32: fix wrong loop bound in flush_cache()

2011-09-03T01:43:45+00:00

The issue is found when calling flush_cache() with zero "size" argument.
The bound of loop is miscalculated in this case and flush_cache() enters
a wrong flushing loop.

Signed-off-by: Yao Cheng 
Cc: Shinya Kuribayashi 
Cc: Sergei Shtylyov 
Cc: Mike Frysinger 
Signed-off-by: Shinya Kuribayashi

MIPS: make cache operation mode configurable

2011-07-31T14:26:41+00:00

Currently the cache operation mode is hard-coded to
CONF_CM_CACHABLE_NONCOHERENT. This is not appropiate for CPUs or SOCs
which operate at a different mode.

This patch makes the cache operation mode configurable via board config.

Signed-off-by: Daniel Schwierzeck 
Acked-by: Thomas Langer 
Signed-off-by: Shinya Kuribayashi

MIPS: rename INFINEON_EBU_BOOTCFG to CONFIG_SYS_XWAY_EBU_BOOTFG

2011-07-31T14:26:41+00:00

This define is a board-specific config option and should be
renamed to follow the U-Boot naming convention. Additionally,
add an explaining comment for this option.

Signed-off-by: Daniel Schwierzeck 
Acked-by: Thomas Langer 
Signed-off-by: Shinya Kuribayashi

unify version_string

2011-07-28T15:22:53+00:00

This patch removes the architecture specific implementation of
version_string where possible. Some architectures use a special place
and therefore we provide U_BOOT_VERSION_STRING definition and a common
weak symbol version_string.

Signed-off-by: Andreas Bie�mann 
CC: Mike Frysinger 
CC: Peter Pan 
Acked-by: Mike Frysinger

Timer: Remove reset_timer() for non-Nios2 arches

2011-07-26T12:53:30+00:00

Timer: Remove set_timer completely

2011-07-26T12:52:17+00:00

MIPS: Move timer code to arch/mips/cpu/$(CPU)/

2011-05-09T15:12:31+00:00

Current timer routines (arch/mips/lib/timer.c) are implemented assuming
that MIPS32 coprocessor (CP0) resources, Counter and Compare registers
in this case, are available.  But this doesn't always work.

We need to make sure that all MIPS-based systems don't necessarily use
CP0 counter/compare registers as time keeping resources.  And some MIPS
variant processors might come with different hardware specs with genuine
MIPS32 CP0 registers.

With this change, each $(CPU)/ directory can have its own timer code.

Signed-off-by: Shinya Kuribayashi

MIPS: Introduce --gc-sections for MIPS

2011-05-09T15:08:10+00:00

All architectures but MIPS are using --gc-sections on final linking.
This patch introduces that feature for MIPS to reduce the memory and
flash footprint.

Signed-off-by: Daniel Schwierzeck 
Cc: Wolfgang Denk 
Cc: Stefan Roese 
Cc: Thomas Lange 
Cc: Vlad Lungu 
Signed-off-by: Shinya Kuribayashi

MIPS: Coding style cleanups on common assembly files

2011-05-06T15:18:13+00:00

Fix style issues and alignments globally.  No logical changes.
- Replace C comments with AS line comments where possible
- Use ifndef where possible, rather than if !defined for simplicity
- An instruction executed in a delay slot is now indicated by a leading
  space, not by C comment

Signed-off-by: Shinya Kuribayashi

MIPS: Remove mips_cache_lock() feature

2011-05-06T15:18:13+00:00

As requested in commit e1390801a3c1a2b6d12fa90be368efc19f5b9bfd ([MIPS]
Request for the 'mips_cache_lock()' removal), such feature is no longer
needed for current MIPS implementation of U-Boot, and no one in the tree
uses it for years.

Signed-off-by: Shinya Kuribayashi