u-boot.git/arch/mips, branch v2016.07-rc1

mips: ath79: Use AR933X_PLL_SWITCH_CLOCK_CONTROL_REG macro define

2016-05-31T08:17:54Z

Add AR933X_PLL_SWITCH_CLOCK_CONTROL_REG define for ar933x chip. Signed-off-by: Wills Wang

mips: ath79: Add support for ungating USB and ethernet on qca953x

2016-05-31T08:17:54Z

Add code to ungate USB and ethernet controller on qca953x Signed-off-by: Wills Wang

mips: ath79: ap121: Enable ethernet

2016-05-31T08:17:54Z

This patch enable network function for ap121 board. Signed-off-by: Wills Wang Acked-by: Marek Vasut

mips: ath79: Rename get_bootstrap into ath79_get_bootstrap

2016-05-31T08:17:54Z

Add a platform prefix for function name in order to make more readable, and move it into ath79.h Signed-off-by: Wills Wang Acked-by: Marek Vasut

MIPS: Abstract cache op loops with a macro

2016-05-31T07:44:24Z

The various cache maintenance routines perform a number of loops over cache lines. Rather than duplicate the code for performing such loops, abstract it out into a new cache_loop macro which performs an arbitrary number of cache ops on a range of addresses. This reduces duplication in the existing L1 cache maintenance code & will allow for not adding further duplication when introducing L2 cache support. Signed-off-by: Paul Burton

MIPS: Split I & D cache line size config

2016-05-31T07:44:24Z

Allow L1 Icache & L1 Dcache line size to be specified separately, since there's no architectural mandate that they be the same. The [id]cache_line_size functions are tidied up to take advantage of the fact that the Kconfig entries are always present to simply check them for zero rather than needing to #ifdef on their presence. Signed-off-by: Paul Burton [removed CONFIG_SYS_CACHELINE_SIZE in include/configs/pic32mzdask.h] Signed-off-by: Daniel Schwierzeck

MIPS: Move cache sizes to Kconfig

2016-05-31T07:44:24Z

Move details of the L1 cache line sizes & total sizes into Kconfig, defaulting to 0. A new CONFIG_SYS_CACHE_SIZE_AUTO Kconfig entry is introduced to allow platforms to select auto-detection of cache sizes, and it defaults to being enabled if none of the cache sizes are set by the configuration (ie. sizes are all the default 0), and code is adjusted to #ifdef on that rather than on the definition of the sizes (which will always be defined even if 0). Signed-off-by: Paul Burton

MIPS: remove dead code from asm/u-boot-mips.h

2016-05-31T07:38:11Z

Those wrappers for linker symbols were once used in the MIPS specific board.c implementation. Since the migration to generic board.c, those wrappers are dead code and can be removed. Signed-off-by: Daniel Schwierzeck

MIPS: add tune for MIPS 34kc

2016-05-31T07:38:11Z

Add tune Kconfig option for MIPS 34kc. Signed-off-by: Daniel Schwierzeck

MIPS: provide a default u-boot-spl.lds

2016-05-31T07:38:11Z

Provide a default linker script for SPL binaries. Start address and size of text section and BSS section are configurable. All sections are arranged in a way that only relevant sections are kept in the code section for maximum size reduction. All other sections are kept but moved outside the code section to help with debugging. Signed-off-by: Daniel Schwierzeck Acked-by: Marek Vasut