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<title>u-boot.git/arch/mips, branch v2016.09</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>net: mii: Use spatch to update miiphy_register</title>
<updated>2016-08-15T20:26:33+00:00</updated>
<author>
<name>Joe Hershberger</name>
<email>joe.hershberger@ni.com</email>
</author>
<published>2016-08-08T16:28:38+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=5a49f17481bb9dcab1431c663d35cc1cace16825'/>
<id>5a49f17481bb9dcab1431c663d35cc1cace16825</id>
<content type='text'>
Run scripts/coccinelle/net/mdio_register.cocci on the U-Boot code base.

Signed-off-by: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
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<pre>
Run scripts/coccinelle/net/mdio_register.cocci on the U-Boot code base.

Signed-off-by: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>libfdt: Introduce new ARCH_FIXUP_FDT option</title>
<updated>2016-08-01T01:37:08+00:00</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@xilinx.com</email>
</author>
<published>2016-07-28T07:06:41+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=e2f88dfd2d9671945877daf5a8c9223b864c34d1'/>
<id>e2f88dfd2d9671945877daf5a8c9223b864c34d1</id>
<content type='text'>
Add new Kconfig option to disable arch_fixup_fdt() calls for cases where
U-Boot shouldn't update memory setup in DTB file.
One example of usage of this option is to boot OS with different memory
setup than U-Boot use.

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
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<pre>
Add new Kconfig option to disable arch_fixup_fdt() calls for cases where
U-Boot shouldn't update memory setup in DTB file.
One example of usage of this option is to boot OS with different memory
setup than U-Boot use.

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: convert API to match reset/mailbox style</title>
<updated>2016-06-19T23:05:55+00:00</updated>
<author>
<name>Stephen Warren</name>
<email>swarren@nvidia.com</email>
</author>
<published>2016-06-17T15:44:00+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=135aa95002646c46e89de93fa36adad1b010548f'/>
<id>135aa95002646c46e89de93fa36adad1b010548f</id>
<content type='text'>
The following changes are made to the clock API:
* The concept of "clocks" and "peripheral clocks" are unified; each clock
  provider now implements a single set of clocks. This provides a simpler
  conceptual interface to clients, and better aligns with device tree
  clock bindings.
* Clocks are now identified with a single "struct clk", rather than
  requiring clients to store the clock provider device and clock identity
  values separately. For simple clock consumers, this isolates clients
  from internal details of the clock API.
* clk.h is split so it only contains the client/consumer API, whereas
  clk-uclass.h contains the provider API. This aligns with the recently
  added reset and mailbox APIs.
* clk_ops .of_xlate(), .request(), and .free() are added so providers
  can customize these operations if needed. This also aligns with the
  recently added reset and mailbox APIs.
* clk_disable() is added.
* All users of the current clock APIs are updated.
* Sandbox clock tests are updated to exercise clock lookup via DT, and
  clock enable/disable.
* rkclk_get_clk() is removed and replaced with standard APIs.

Buildman shows no clock-related errors for any board for which buildman
can download a toolchain.

test/py passes for sandbox (which invokes the dm clk test amongst
others).

Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
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<pre>
The following changes are made to the clock API:
* The concept of "clocks" and "peripheral clocks" are unified; each clock
  provider now implements a single set of clocks. This provides a simpler
  conceptual interface to clients, and better aligns with device tree
  clock bindings.
* Clocks are now identified with a single "struct clk", rather than
  requiring clients to store the clock provider device and clock identity
  values separately. For simple clock consumers, this isolates clients
  from internal details of the clock API.
* clk.h is split so it only contains the client/consumer API, whereas
  clk-uclass.h contains the provider API. This aligns with the recently
  added reset and mailbox APIs.
* clk_ops .of_xlate(), .request(), and .free() are added so providers
  can customize these operations if needed. This also aligns with the
  recently added reset and mailbox APIs.
* clk_disable() is added.
* All users of the current clock APIs are updated.
* Sandbox clock tests are updated to exercise clock lookup via DT, and
  clock enable/disable.
* rkclk_get_clk() is removed and replaced with standard APIs.

Buildman shows no clock-related errors for any board for which buildman
can download a toolchain.

test/py passes for sandbox (which invokes the dm clk test amongst
others).

Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>MIPS: Make CONFIG_SYS_DCACHE_LINE_SIZE int, not hex</title>
<updated>2016-06-10T10:27:37+00:00</updated>
<author>
<name>Paul Burton</name>
<email>paul.burton@imgtec.com</email>
</author>
<published>2016-06-09T12:09:52+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=4b7b0a0f0635c1d1e4a0ae2ed172530b5f78e74b'/>
<id>4b7b0a0f0635c1d1e4a0ae2ed172530b5f78e74b</id>
<content type='text'>
For consistency with the other cache-related Kconfig entries &amp; the
values actually set by boards, make CONFIG_SYS_DCACHE_LINE_SIZE an int
entry instead of a hex entry.

Signed-off-by: Paul Burton &lt;paul.burton@imgtec.com&gt;
Fixes: 372286217f05 ("MIPS: Split I &amp; D cache line size config")
</content>
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<pre>
For consistency with the other cache-related Kconfig entries &amp; the
values actually set by boards, make CONFIG_SYS_DCACHE_LINE_SIZE an int
entry instead of a hex entry.

Signed-off-by: Paul Burton &lt;paul.burton@imgtec.com&gt;
Fixes: 372286217f05 ("MIPS: Split I &amp; D cache line size config")
</pre>
</div>
</content>
</entry>
<entry>
<title>MIPS: Fix invalidate_dcache_range to operate on L1 Dcache</title>
<updated>2016-06-10T10:27:29+00:00</updated>
<author>
<name>Paul Burton</name>
<email>paul.burton@imgtec.com</email>
</author>
<published>2016-06-09T12:09:51+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=a95800e881a8df837f0c4121a2cd560a4c02bd2f'/>
<id>a95800e881a8df837f0c4121a2cd560a4c02bd2f</id>
<content type='text'>
Commit fb64cda57998 ("MIPS: Abstract cache op loops with a macro")
accidentally modified invalidate_dcache_range to operate on the L1
Icache instead of the Dcache. Fix the cache op used to operate on the
Dcache.

Signed-off-by: Paul Burton &lt;paul.burton@imgtec.com&gt;
Fixes: fb64cda57998 ("MIPS: Abstract cache op loops with a macro")
</content>
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<pre>
Commit fb64cda57998 ("MIPS: Abstract cache op loops with a macro")
accidentally modified invalidate_dcache_range to operate on the L1
Icache instead of the Dcache. Fix the cache op used to operate on the
Dcache.

Signed-off-by: Paul Burton &lt;paul.burton@imgtec.com&gt;
Fixes: fb64cda57998 ("MIPS: Abstract cache op loops with a macro")
</pre>
</div>
</content>
</entry>
<entry>
<title>mips: ath79: Use AR933X_PLL_SWITCH_CLOCK_CONTROL_REG macro define</title>
<updated>2016-05-31T08:17:54+00:00</updated>
<author>
<name>Wills Wang</name>
<email>wills.wang@live.com</email>
</author>
<published>2016-05-30T14:54:54+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ca09e66b04cd2b80f95d5acc1cc7f61487034faf'/>
<id>ca09e66b04cd2b80f95d5acc1cc7f61487034faf</id>
<content type='text'>
Add AR933X_PLL_SWITCH_CLOCK_CONTROL_REG define for ar933x chip.

Signed-off-by: Wills Wang &lt;wills.wang@live.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add AR933X_PLL_SWITCH_CLOCK_CONTROL_REG define for ar933x chip.

Signed-off-by: Wills Wang &lt;wills.wang@live.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>mips: ath79: Add support for ungating USB and ethernet on qca953x</title>
<updated>2016-05-31T08:17:54+00:00</updated>
<author>
<name>Wills Wang</name>
<email>wills.wang@live.com</email>
</author>
<published>2016-05-30T14:54:53+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=cdeb68e292358f9dedeaea167f6eba894c58823e'/>
<id>cdeb68e292358f9dedeaea167f6eba894c58823e</id>
<content type='text'>
Add code to ungate USB and ethernet controller on qca953x

Signed-off-by: Wills Wang &lt;wills.wang@live.com&gt;
</content>
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<pre>
Add code to ungate USB and ethernet controller on qca953x

Signed-off-by: Wills Wang &lt;wills.wang@live.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>mips: ath79: ap121: Enable ethernet</title>
<updated>2016-05-31T08:17:54+00:00</updated>
<author>
<name>Wills Wang</name>
<email>wills.wang@live.com</email>
</author>
<published>2016-05-30T14:54:51+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=04583c686e61e6883158549603d60741ebf249fe'/>
<id>04583c686e61e6883158549603d60741ebf249fe</id>
<content type='text'>
This patch enable network function for ap121 board.

Signed-off-by: Wills Wang &lt;wills.wang@live.com&gt;
Acked-by: Marek Vasut &lt;marex@denx.de&gt;
</content>
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<pre>
This patch enable network function for ap121 board.

Signed-off-by: Wills Wang &lt;wills.wang@live.com&gt;
Acked-by: Marek Vasut &lt;marex@denx.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>mips: ath79: Rename get_bootstrap into ath79_get_bootstrap</title>
<updated>2016-05-31T08:17:54+00:00</updated>
<author>
<name>Wills Wang</name>
<email>wills.wang@live.com</email>
</author>
<published>2016-05-30T14:54:50+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=375239174c6bc6a9966db333fa79f578154828f5'/>
<id>375239174c6bc6a9966db333fa79f578154828f5</id>
<content type='text'>
Add a platform prefix for function name in order to make more readable,
and move it into ath79.h

Signed-off-by: Wills Wang &lt;wills.wang@live.com&gt;
Acked-by: Marek Vasut &lt;marex@denx.de&gt;
</content>
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<pre>
Add a platform prefix for function name in order to make more readable,
and move it into ath79.h

Signed-off-by: Wills Wang &lt;wills.wang@live.com&gt;
Acked-by: Marek Vasut &lt;marex@denx.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>MIPS: Abstract cache op loops with a macro</title>
<updated>2016-05-31T07:44:24+00:00</updated>
<author>
<name>Paul Burton</name>
<email>paul.burton@imgtec.com</email>
</author>
<published>2016-05-27T13:28:06+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=fb64cda579985e21610672eae44faf40eadd71ea'/>
<id>fb64cda579985e21610672eae44faf40eadd71ea</id>
<content type='text'>
The various cache maintenance routines perform a number of loops over
cache lines. Rather than duplicate the code for performing such loops,
abstract it out into a new cache_loop macro which performs an arbitrary
number of cache ops on a range of addresses. This reduces duplication in
the existing L1 cache maintenance code &amp; will allow for not adding
further duplication when introducing L2 cache support.

Signed-off-by: Paul Burton &lt;paul.burton@imgtec.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The various cache maintenance routines perform a number of loops over
cache lines. Rather than duplicate the code for performing such loops,
abstract it out into a new cache_loop macro which performs an arbitrary
number of cache ops on a range of addresses. This reduces duplication in
the existing L1 cache maintenance code &amp; will allow for not adding
further duplication when introducing L2 cache support.

Signed-off-by: Paul Burton &lt;paul.burton@imgtec.com&gt;
</pre>
</div>
</content>
</entry>
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