u-boot.git/arch/mips, branch v2017.01

libfdt: replace ARCH_FIXUP_FDT with ARCH_FIXUP_FDT_MEMORY

2016-12-03T03:54:34+00:00

Commit e2f88dfd2d96 ("libfdt: Introduce new ARCH_FIXUP_FDT option")
allows us to skip memory setup of DTB, but a problem for ARM is that
spin_table_update_dt() and psci_update_dt() are skipped as well if
CONFIG_ARCH_FIXUP_FDT is disabled.

This commit allows us to skip only fdt_fixup_memory_banks() instead
of the whole of arch_fixup_fdt().  It will be useful when we want to
use a memory node from a kernel DTB as is, but need some fixups for
Spin-Table/PSCI.

Signed-off-by: Masahiro Yamada 
Acked-by: Alexey Brodkin 
Acked-by: Simon Glass 
Fixed build error for x86:
Signed-off-by: Simon Glass

MIPS: Fix map_physmem for cached mappings

2016-11-30T15:18:19+00:00

map_physmem should return a pointer that can be used by the CPU to
access the given memory - on MIPS simply returning the physical address
as it does prior to this patch doesn't achieve that. Instead return a
pointer to the memory within (c)kseg0, which matches up consistently
with the (c)kseg1 pointer that uncached mappings return via ioremap.

Signed-off-by: Paul Burton

MIPS: Use ram_top, not bi_memsize, in arch_lmb_reserve

2016-11-30T15:15:51+00:00

When calculating the region to reserve for the stack in
arch_lmb_reserve, make use of ram_top instead of adding bi_memsize to
CONFIG_SYS_SDRAM_BASE. This avoids overflow if the system has enough
memory to reach the end of the address space.

Signed-off-by: Paul Burton

mips: Let cache.h be included from assembly source

2016-11-30T15:13:17+00:00

Add ifdef __ASSEMBLY__ around the function prototype to let cache.h
be included from assembly code.

Signed-off-by: Marek Vasut 
Cc: Daniel Schwierzeck 
Cc: Paul Burton

MIPS: add handling for generic and EJTAG exceptions

2016-11-30T15:12:17+00:00

Add exception handlers for generic and EJTAG exceptions. Most of
the assembly code is imported from Linux kernel and adapted to U-Boot.
The exception vector table will be reserved above the stack before
U-Boot is relocated. The exception handlers will be installed and
activated after relocation in the initr_traps hook function.

Generic exceptions are handled by showing a CPU register dump similar
to Linux kernel. For example:

malta # md 1
00000001:
Ooops:
$ 0   : 00000000 00000000 00000009 00000004
$ 4   : 8ff7e108 00000000 0000003a 00000000
$ 8   : 00000008 00000001 8ff7cd18 00000004
$12   : 00000002 00000000 00000005 0000003a
$16   : 00000004 00000040 00000001 00000001
$20   : 00000000 8fff53c0 00000008 00000004
$24   : ffffffff 8ffdea44
$28   : 90001650 8ff7cd00 00000004 8ffe6818
Hi    : 00000000
Lo    : 00000004
epc   : 8ffe6848 (text bfc28848)
ra    : 8ffe6818 (text bfc28818)
Status: 00000006
Cause : 00000410 (ExcCode 04)
BadVA : 8ff9e928
PrId  : 00019300
 ### ERROR ### Please RESET the board ###

EJTAG exceptions are checked for SDBBP and delegated to the SDBBP handler
if necessary. Otherwise the debug mode will simply be exited. The SDBBP
handler currently prints the contents of registers c0_depc and c0_debug.
This could be extended in the future to handle semi-hosting according to
the MIPS UHI specification.

Signed-off-by: Daniel Schwierzeck 
Reviewed-by: Paul Burton 
Tested-by: Paul Burton

MIPS: reserve space for exception vectors

2016-11-30T15:11:46+00:00

In order to set own exception handlers, a table with the exception
vectors must be built in DRAM and the CPU EBase register must be
set to the base address of this table.

Reserve the space above the stack and use gd->irq_sp as storage
for the exception base address.

Signed-off-by: Daniel Schwierzeck

MIPS: add asm-offsets for struct pt_regs

2016-11-30T15:11:46+00:00

Import asm-offsets.c from kernel to generate offset for struct pt_regs
needed by exception handlers.

Signed-off-by: Daniel Schwierzeck

MIPS: add possibility to setup initial stack and global data in SRAM

2016-11-30T15:11:46+00:00

This adds a new Kconfig option CONFIG_MIPS_INIT_STACK_IN_SRAM which
a SoC can select if it supports some kind of SRAM. Together with
CONFIG_SYS_INIT_SP_ADDR the initial stack and global data can be
set up in that SRAM. This can be used to provide a C environment
also for lowlevel_init().

Signed-off-by: Daniel Schwierzeck

MIPS: factor out code for initial stack and global data

2016-11-30T15:11:46+00:00

Move the code for setting up the initial stack and global data
to a macro to be able to use it more than once.

Signed-off-by: Daniel Schwierzeck

MIPS: fix iand optimize setup of CP0 registers

2016-11-30T15:11:46+00:00

Clear cp0 status while preserving implementation specific bits.
Set bits BEV and ERL as the arch specification requires after
a reset or soft-reset exception.

Extend and fix initialization of watch registers. Check if additional
watch register sets are implemented and initialize them too.

Initialize cp0 count as early as possible to get the most
accurate boot timing.

Signed-off-by: Daniel Schwierzeck