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<title>u-boot.git/arch/mips, branch v2025.07</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/mips?h=v2025.07</id>
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<updated>2025-05-06T21:43:19Z</updated>
<entry>
<title>mips: octeon: remove unused middle expression</title>
<updated>2025-05-06T21:43:19Z</updated>
<author>
<name>Bryan Brattlof</name>
<email>bb@ti.com</email>
</author>
<published>2025-04-09T17:26:20Z</published>
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<id>urn:sha1:13d1bd5bbbfaf725a4c159851203d658c1de83ba</id>
<content type='text'>
!A || (A &amp;&amp; B) is equivalent to !A || B

Drop the unused middle expression to simplify the statement.

Signed-off-by: Bryan Brattlof &lt;bb@ti.com&gt;
Reviewed-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
</content>
</entry>
<entry>
<title>Merge patch series "MIPS: Boston: Various enhancements"</title>
<updated>2025-04-22T21:13:21Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2025-04-22T21:13:21Z</published>
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<id>urn:sha1:20fcb6305eef553a94eeed6efb1a60ee3ccd9db7</id>
<content type='text'>
Jiaxun Yang &lt;jiaxun.yang@flygoat.com&gt; says:

This is a huge series which promoted MIPS/Boston target into a
usable state, with fixes to drivers and general framework issues
I found in this process.

I also converted the target to OF_UPSTREAM.

This target is covered by QEMU, to test on QEMU:
```
make boston64r6el_defconfig
make
qemu-system-mips64el -M boston -cpu I6500 -bios ./u-boot.bin -nographic
```

Link: https://lore.kernel.org/r/20240517-boston-v3-0-1ea7d23f4a1d@flygoat.com
</content>
</entry>
<entry>
<title>MIPS: boston: Migrate to OF_UPSTREAM</title>
<updated>2025-04-22T21:08:47Z</updated>
<author>
<name>Jiaxun Yang</name>
<email>jiaxun.yang@flygoat.com</email>
</author>
<published>2024-05-17T18:14:59Z</published>
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<id>urn:sha1:4ba5026a0fb4a4a3825e250d8e76f07b5a5e4609</id>
<content type='text'>
We can now boot with upstream devicetree.

Reviewed-by: Sumit Garg &lt;sumit.garg@linaro.org&gt;
Signed-off-by: Jiaxun Yang &lt;jiaxun.yang@flygoat.com&gt;
Reviewed-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
</content>
</entry>
<entry>
<title>MIPS: boston: Imply various options</title>
<updated>2025-04-22T21:08:47Z</updated>
<author>
<name>Jiaxun Yang</name>
<email>jiaxun.yang@flygoat.com</email>
</author>
<published>2024-05-17T18:14:55Z</published>
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<id>urn:sha1:49cc0e1adceeeb8f149390e45a0aa8fa0c1e4ef4</id>
<content type='text'>
This is a PC-like platform board.
Enable drivers for most on-board devices to make it useful.

Signed-off-by: Jiaxun Yang &lt;jiaxun.yang@flygoat.com&gt;
Reviewed-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
</content>
</entry>
<entry>
<title>MIPS: Provide dummy acpi_table.h</title>
<updated>2025-04-22T21:08:47Z</updated>
<author>
<name>Jiaxun Yang</name>
<email>jiaxun.yang@flygoat.com</email>
</author>
<published>2024-05-17T18:14:54Z</published>
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<id>urn:sha1:0fd4686df5fe7a7b1783eec6ff21ffdd1c2b0467</id>
<content type='text'>
Some drivers need this header.
Provide this dummy header as riscv did.

Signed-off-by: Jiaxun Yang &lt;jiaxun.yang@flygoat.com&gt;
Reviewed-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
</content>
</entry>
<entry>
<title>mips: malta: set MIPS_RELOCATION_TABLE_SIZE=0xc000</title>
<updated>2025-04-19T10:50:04Z</updated>
<author>
<name>Heinrich Schuchardt</name>
<email>heinrich.schuchardt@canonical.com</email>
</author>
<published>2024-11-03T19:01:13Z</published>
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<id>urn:sha1:ed16466966447b95d402376035217633ee5098ad</id>
<content type='text'>
MIPS_RELOCATION_TABLE_SIZE=0x8000 is too small to enable UNIT_TEST.
Increase it by 50 % (16 KiB).

Signed-off-by: Heinrich Schuchardt &lt;heinrich.schuchardt@canonical.com&gt;
</content>
</entry>
<entry>
<title>x86: select CONFIG_64BIT for X86_64</title>
<updated>2024-12-31T16:58:30Z</updated>
<author>
<name>Andrew Goodbody</name>
<email>andrew.goodbody@linaro.org</email>
</author>
<published>2024-12-16T18:07:35Z</published>
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<id>urn:sha1:99145eec2dca317da6b48d0f8fdd602001f87e61</id>
<content type='text'>
Select CONFIG_64BIT so that we pass the -m64 option (instead of -m32) to
static analysis tools.
Introduce CONFIG_SPL_64BIT and select it for architectures other than
x86 with 64 bit builds. Do not select it for x86 builds as x86 uses
a 32 bit SPL.
Ensure that when limits are set they use CONFIG_64BIT for U-Boot
proper and CONFIG_SPL_64BIT for SPL. This is to allow for the 32 bit
SPL build used by x86.

Signed-off-by: Dan Carpenter &lt;dan.carpenter@linaro.org&gt;
Signed-off-by: Andrew Goodbody &lt;andrew.goodbody@linaro.org&gt;
</content>
</entry>
<entry>
<title>CONFIG_SYS_NONCACHED_MEMORY: Move prototypes to include/cpu_func.h for consistency</title>
<updated>2024-10-29T22:17:18Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2024-10-22T16:31:17Z</published>
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<id>urn:sha1:17e476aa0525905c52e48c19adcb54fdca60d48b</id>
<content type='text'>
Currently, a number of generic cache related functions have their common
prototype declared in include/cpu_func.h. Move the current set of
noncached functions there as well to match.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>dts: Deduplicate dtbs target</title>
<updated>2024-10-15T01:32:04Z</updated>
<author>
<name>Marek Vasut</name>
<email>marex@denx.de</email>
</author>
<published>2024-10-04T00:10:42Z</published>
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<id>urn:sha1:d2061828a4c1b60b44cd2307b6a782ac2efbffbe</id>
<content type='text'>
The dtbs: target is almost identical in all architecture Makefiles.
All architecture Makefiles include scripts/Makefile.dts . Deduplicate
the dtbs: target into scripts/Makefile.dts . No functional change.

Reviewed-by: Sumit Garg &lt;sumit.garg@linaro.org&gt;
Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested-by: Caleb Connolly &lt;caleb.connolly@linaro.org&gt; #qcom, OF_UPSTREAM
</content>
</entry>
<entry>
<title>arch: Use CONFIG_XPL_BUILD instead of CONFIG_SPL_BUILD</title>
<updated>2024-10-11T17:44:47Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2024-09-30T01:49:46Z</published>
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<id>urn:sha1:bef9fdbed2e525ce9264d2ae2fbcb37db7472052</id>
<content type='text'>
Use the new symbol to refer to any 'SPL' build, including TPL and VPL

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
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