u-boot.git/arch/powerpc/cpu/mpc85xx/cmd_errata.c, branch v2011.06

powerpc/85xx: Implement work-around for P4080 erratum SERDES-A005

2011-04-29T03:09:23Z

SerDes PLL bandwidth default setting is incorrect when no lanes are configured as PCI Express. Signed-off-by: Timur Tabi Signed-off-by: Kumar Gala

p4080/serdes: Implement the XAUI workaround for SERDES9 erratum

2011-04-28T03:29:04Z

Signed-off-by: Emil Medve Signed-off-by: Timur Tabi Signed-off-by: Kumar Gala

powerpc/mpc85xx: implement workaround for errata DDR111 and DDR134

2011-02-03T08:46:13Z

Workaround for the following errata: DDR111 - MCKE signal may not function correctly at assertion of HRESET DDR134 - The automatic CAS-to-Preamble feature of the DDR controller can calibrate to incorrect values These two workarounds must be implemented together because they touch common registers. Signed-off-by: York Sun Signed-off-by: Kumar Gala

powerpc/85xx: Rename MPC8572 DDR erratum to DDR115

2011-02-03T08:46:13Z

Use unique erratum number instead of platform number. Enable command that reports errata on MPC8572DS. Signed-off-by: York Sun Signed-off-by: Kumar Gala

fsl_esdhc: Add the workaround for erratum ESDHC-A001 (enable on P2020)

2011-02-03T08:46:12Z

Data timeout counter (SYSCTL[DTOCV]) is not reliable for values of 4, 8, and 12. Program one more than the desired value: 4 -> 5, 8 -> 9, 12 -> 13. Signed-off-by: Kumar Gala

mpc85xx: Implement workaround for erratum DDR-A003

2011-01-20T04:58:24Z

Erratum DDR-A003 requires workaround to correctly set RCW10 for registered DIMM. Also adding polling after enabling DDR controller to ensure completion. Signed-off-by: York Sun Signed-off-by: Kumar Gala

powerpc/85xx: Add the workaround for erratum ELBC-A001 (enable on P4080)

2011-01-14T07:32:22Z

Simultaneous FCM and GPCM or UPM operation may erroneously trigger bus monitor timeout. Set timeout to maximum to avoid. Based on a patch from Lan Chunhe Signed-off-by: Kumar Gala

powerpc/85xx: Add the workaround for erratum CPC-A003 (enable on P4080)

2011-01-14T07:32:22Z

CoreNet Platform Cache single-bit data error scrubbing will cause data corruption. Disable the feature to workaround the issue. Signed-off-by: Kumar Gala

powerpc/85xx: Add the workaround for erratum CPC-A002 (enable on P4080)

2011-01-14T07:32:22Z

CoreNet Platform Cache single-bit tag error scrubbing will cause tag corruption. Disable the feature to workaround the issue. Signed-off-by: Kumar Gala

fsl_esdhc: Add the workaround for erratum ESDHC136 (enable on P4080)

2011-01-14T07:32:22Z

False multi-bit ECC errors will be reported by the eSDHC buffer which can trigger a reset request. We disable all ECC error checking on SDHC. Signed-off-by: Roy Zang Signed-off-by: Kumar Gala