u-boot.git/arch/powerpc/cpu/mpc85xx/cpu_init.c, branch v2011.06

powerpc/85xx: Enable Internal USB PHY for p2040, p3041, p5010 and p5020

2011-04-28T03:29:04Z

The P2040, P3041, P5010, and P5020 all have internal USB PHYs that we need to enable for them to function. Signed-off-by: Roy Zang Signed-off-by: Kumar Gala

powerpc/85xx: Add PBL boot from SPI flash support on P4080DS

2011-04-10T16:17:55Z

PBL(pre-boot loader): SPI flash used as RCW(Reset Configuration Word) and PBI(pre-boot initialization) source, CPC(CoreNet Platform Cache) used as 1M SRAM where PBL will copy whole U-BOOT image to, U-boot can boot from CPC after PBL completes RCW and PBI phases. Signed-off-by: Chunhe Lan Signed-off-by: Mingkai Hu Signed-off-by: Shaohui Xie Signed-off-by: Roy Zang Signed-off-by: Kumar Gala

powerpc/85xx: load ucode from nand flash before qe_init

2011-04-04T14:24:41Z

In the case the QE's microcode is stored in nand flash, we need to load it from NAND flash to ddr first then the qe_init can get the ucode correctly. Signed-off-by: Haiying Wang Signed-off-by: Kumar Gala

powerpc: Add cpu_secondary_init_r to allow for initialization post env setup

2011-04-04T14:24:41Z

We can simplify some cpu/SoC level initialization by moving it to be after the environment and non-volatile storage is setup as there might be dependancies on such things in various boot configurations. For example for FSL SoC's with QE if we boot from NAND we need it setup to extra the ucode image to initialize the QE. If we always do this after environment & non-volatile storage is working we can have the code be the same regardless of NOR, NAND, SPI, MMC boot. Signed-off-by: Kumar Gala

powerpc/85xx: Add the workaround for erratum CPC-A003 (enable on P4080)

2011-01-14T07:32:22Z

CoreNet Platform Cache single-bit data error scrubbing will cause data corruption. Disable the feature to workaround the issue. Signed-off-by: Kumar Gala

powerpc/85xx: Add the workaround for erratum CPC-A002 (enable on P4080)

2011-01-14T07:32:22Z

CoreNet Platform Cache single-bit tag error scrubbing will cause tag corruption. Disable the feature to workaround the issue. Signed-off-by: Kumar Gala

fsl_esdhc: Add the workaround for erratum ESDHC136 (enable on P4080)

2011-01-14T07:32:22Z

False multi-bit ECC errors will be reported by the eSDHC buffer which can trigger a reset request. We disable all ECC error checking on SDHC. Signed-off-by: Roy Zang Signed-off-by: Kumar Gala

powerpc/8xxx: Refactor SRIO initialization into common code

2011-01-14T07:32:21Z

Moved the SRIO init out of corenet_ds and into common code for 8xxx/QorIQ processors that have SRIO. We mimic what we do with PCIe controllers for SRIO. We utilize the fact that SRIO is over serdes to determine if its configured or not and thus can setup the LAWs needed for it dynamically. We additionally update the device tree (to remove the SRIO nodes) if the board doesn't have SRIO enabled. Introduced the following standard defines for board config.h: CONFIG_SYS_SRIO - Chip has SRIO or not CONFIG_SRIO1 - Board has SRIO 1 port available CONFIG_SRIO2 - Board has SRIO 2 port available (where 'n' is the port #) CONFIG_SYS_SRIOn_MEM_VIRT - virtual address in u-boot CONFIG_SYS_SRIOn_MEM_PHYS - physical address (for law setup) CONFIG_SYS_SRIOn_MEM_SIZE - size of window (for law setup) [ These mimic what we have for PCI and PCIe controllers ] Signed-off-by: Kumar Gala Acked-by: Wolfgang Denk

powerpc/85xx: Replace CONFIG_SYS_HAS_SERDES with a weak function

2011-01-14T07:32:18Z

Instead of a #define use a null weak function for fsl_serdes_init Signed-off-by: Kumar Gala

powerpc/85xx: do not reloc l2srbar if CONFIG_FLASH_BASE is not defined

2010-12-01T16:01:14Z

This fixes the compiling error for the board which doesn't have NOR flash (so CONFIG_FLASH_BASE is not defined) Signed-off-by: Haiying Wang Signed-off-by: Kumar Gala