u-boot.git/arch/powerpc/cpu/mpc85xx, branch v2011.06

Minor coding style cleanup.

2011-05-19T20:22:44Z

Signed-off-by: Wolfgang Denk

powerpc/85xx: fix compatible property for the L2 cache node

2011-05-13T05:36:11Z

The compatible property for the L2 cache node (on 85xx systems that don't have a CPC) was using a value for the property length that did not match the actual length of the property. Signed-off-by: Timur Tabi Signed-off-by: Kumar Gala

powerpc/85xx: Change timebase divisor to be defined per processor

2011-04-29T03:09:24Z

Introduce new CONFIG_SYS_FSL_TBCLK_DIV on 85xx platforms because different SoCs have different divisor amounts. All the PQ3 parts are /8, the P4080/P4080 is /16, and P2040/P3041/P5020 are /32. Signed-off-by: Kumar Gala

powerpc/85xx: Implement work-around for P4080 erratum SERDES-A001

2011-04-29T03:09:23Z

Bank powerdown through RCW[SRDS_LPD_Bn] for XAUI on FM2 and SGMII on FM1 are swapped. Erratum SERDES-A001 says that if bank two is kept disabled and after bank three is enabled, then the PLL for bank three won't lock properly. The work-around is to enable and then disable bank two after bank three is enabled. Signed-off-by: Timur Tabi Signed-off-by: Kumar Gala

powerpc/85xx: Extend SERDES9 erratum work-around to SGMII, SRIO, and AURORA

2011-04-29T03:09:23Z

Part of the SERDES9 erratum work-around is to set some bits in the SerDes TTLCR0 register for lanes configured as XAUI, SGMII, SRIO, or AURORA. The current code does this only for XAUI, so extend it to the other protocols. Signed-off-by: Timur Tabi Signed-off-by: Kumar Gala

powerpc/85xx: Display SERDES 8 erratum warning if banks are not disabled

2011-04-29T03:09:23Z

The work-around for P4080 erratum SERDES-8 requires all lanes of banks two and three to be disabled (powered down) in the RCW. Display a warning message if this is not the case. Signed-off-by: Timur Tabi Signed-off-by: Kumar Gala

powerpc/85xx: Implement work-around for P4080 erratum SERDES-A005

2011-04-29T03:09:23Z

SerDes PLL bandwidth default setting is incorrect when no lanes are configured as PCI Express. Signed-off-by: Timur Tabi Signed-off-by: Kumar Gala

powerpc/85xx: Enable Internal USB PHY for p2040, p3041, p5010 and p5020

2011-04-28T03:29:04Z

The P2040, P3041, P5010, and P5020 all have internal USB PHYs that we need to enable for them to function. Signed-off-by: Roy Zang Signed-off-by: Kumar Gala

p4080/serdes: Implement the XAUI workaround for SERDES9 erratum

2011-04-28T03:29:04Z

Signed-off-by: Emil Medve Signed-off-by: Timur Tabi Signed-off-by: Kumar Gala

powerpc/85xx: fsl_corenet_serdes code rework

2011-04-28T03:29:04Z

Rework and add some new APIs to the fsl_corenet_serdes code for use by erratum and drivers. * Rename serdes_get_bank() to serdes_get_bank_by_lane() * Add serdes_get_first_lane returns which SERDES lane is used by device Signed-off-by: Emil Medve Signed-off-by: Timur Tabi Signed-off-by: Kumar Gala