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<title>u-boot.git/arch/powerpc/cpu/mpc8xx/Kconfig, branch master</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/powerpc/cpu/mpc8xx/Kconfig?h=master</id>
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<updated>2023-08-09T13:21:42Z</updated>
<entry>
<title>Kconfigs: Correct default of "0" on hex type entries</title>
<updated>2023-08-09T13:21:42Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2023-08-02T15:09:43Z</published>
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<id>urn:sha1:a077ac13d03c8cde646ddab30b03ec0f8b753e1e</id>
<content type='text'>
It is not a parse error to have a default value of "0" for a "hex" type
entry, instead of "0x0".  However, "0" and "0x0" are not treated the
same even by the tools themselves. Correct this by changing the default
value from "0" to "0x0" for all hex type questions that had the
incorrect default. Fix one instance (in two configs) of a default of "0"
being used on a hex question to be "0x0". Remove the cases where a
defconfig had set a value of "0x0" to be used as the default had been
"0".

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>powerpc: mpc8xx: Add SMC relocation CPM microcode</title>
<updated>2023-05-05T05:26:53Z</updated>
<author>
<name>Christophe Leroy</name>
<email>christophe.leroy@csgroup.eu</email>
</author>
<published>2023-05-03T06:57:33Z</published>
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<id>urn:sha1:e7930e93cc6f8d442a86feeaa4c77332a875b02f</id>
<content type='text'>
In order to use QMC mode in the CPM, a SCC requires more space
in parameter RAM.

After SCC1 there is I2C parameter RAM and after SCC2 there is
SPI parameter RAM. MPC866 and MPC885 can already relocate I2C and.
SPI parameter RAM.

But in order to free space after SCC3 and SCC4, SMC1 and SMC2
need to be relocated. In order to do so, a CPM microcode patch
is required.

Binary data for that patch is copied from Linux kernel.

Signed-off-by: Christophe Leroy &lt;christophe.leroy@csgroup.eu&gt;
</content>
</entry>
<entry>
<title>powerpc: mpc885: Add CPM USB-SOF microcode for CPM15 ERRATA</title>
<updated>2023-05-05T05:26:53Z</updated>
<author>
<name>Christophe Leroy</name>
<email>christophe.leroy@csgroup.eu</email>
</author>
<published>2023-05-03T06:50:55Z</published>
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<id>urn:sha1:62c5fae511494590e6b8404c315fe156575a0753</id>
<content type='text'>
MPC885 CPU has the following ERRATA:

	When the USB controller is configured in Host mode, and the
	SOF generation (SFTE=1 in USMOD register) is being used,
	there may be false CRC error indication in other SCCs.
	Although the data is received correctly, the CRC result
	will be corrupted.

Add capability to load the related microcode to fix it.
The microcode binary data is copied from Linux kernel.

Other microcode will be added in following patch so make it
a Kconfig choice.

Signed-off-by: Christophe Leroy &lt;christophe.leroy@csgroup.eu&gt;
</content>
</entry>
<entry>
<title>watchdog: mpc8xxx: Make it generic</title>
<updated>2023-04-06T12:47:47Z</updated>
<author>
<name>Christophe Leroy</name>
<email>christophe.leroy@csgroup.eu</email>
</author>
<published>2023-04-03T08:27:39Z</published>
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<id>urn:sha1:26e8ebcd7cb7eabe2d62384b22d3ed9a235cb60e</id>
<content type='text'>
mpc8xx, mpc83xx and mpc86xx have similar watchdog with almost same
memory registers.

Refactor the driver to get the register addresses from the
device tree and use the compatible to know the prescale factor.

Calculate the watchdog setup value from the provided timeout.

Don't declare it anymore as an HW_WATCHDOG, u-boot will start
servicing the watchdog early enough.

On mpc8xx the watchdog configuration register is also used for
configuring the bus monitor. So add it as an option to the watchdog
when it is mpc8xx. When watchdog is not selected, leave the
configuration of the initial SYPCR from Kconfig.

Signed-off-by: Christophe Leroy &lt;christophe.leroy@csgroup.eu&gt;
</content>
</entry>
<entry>
<title>powerpc: mpc8xx: Migrate to CONFIG_SYS_CLK_FREQ</title>
<updated>2023-04-05T17:46:18Z</updated>
<author>
<name>Christophe Leroy</name>
<email>christophe.leroy@csgroup.eu</email>
</author>
<published>2023-04-04T08:14:33Z</published>
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<id>urn:sha1:9750a245cd4aca96ff01152929bf72004029545c</id>
<content type='text'>
8xx has CONFIG_8xx_GCLK_FREQ which is similar to
CONFIG_SYS_CLK_FREQ, and doesn't set CONFIG_SYS_CLK_FREQ.

Due to that, get_board_sys_clk() returns 0.

Remove CONFIG_8xx_GCLK_FREQ and use CONFIG_SYS_CLK_FREQ instead.

Signed-off-by: Christophe Leroy &lt;christophe.leroy@csgroup.eu&gt;
</content>
</entry>
<entry>
<title>board: cssi: Add new board MCR3000_2G</title>
<updated>2023-02-11T07:47:58Z</updated>
<author>
<name>Christophe Leroy</name>
<email>christophe.leroy@csgroup.eu</email>
</author>
<published>2022-10-14T10:54:50Z</published>
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<id>urn:sha1:dac3c6f625e03be0b5017b0d436c73aeeb1a673e</id>
<content type='text'>
This adds a new board from CS GROUP. The board is called
MCR3000_2G, and has a CPU board called CMPC885.

That CPU board is shared with another equipment that will
be added in a later patch.

That board stores Ethernet MAC addresses in an EEPROM which
is accessed using SPI bus.

This patch was originally written by Charles Frey who's
email address is not valid anymore as he left the company.

Signed-off-by: Christophe Leroy &lt;christophe.leroy@csgroup.eu&gt;
Reviewed-by: FRANJOU Stephane &lt;stephane.franjou@csgroup.eu&gt;
</content>
</entry>
<entry>
<title>board: MCR3000: Use lowercase filenames</title>
<updated>2023-02-10T18:33:25Z</updated>
<author>
<name>Christophe Leroy</name>
<email>christophe.leroy@csgroup.eu</email>
</author>
<published>2023-01-30T08:11:03Z</published>
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<id>urn:sha1:d8809bac482508ea7a961c12f64311d12e8f5594</id>
<content type='text'>
Rename MCR3000.* to mcr3000.* to be more in line with
other boards.

Signed-off-by: Christophe Leroy &lt;christophe.leroy@csgroup.eu&gt;
</content>
</entry>
<entry>
<title>Convert CONFIG_SYS_IMMR to Kconfig</title>
<updated>2021-12-27T13:41:38Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2021-12-13T03:12:30Z</published>
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<id>urn:sha1:be7dbb60c5bfa38ea444fe7de1dca8bd35f83f5b</id>
<content type='text'>
This converts the following to Kconfig:
   CONFIG_SYS_IMMR

We do this by consolidating the SYS_IMMR options we have and providing
defaults.

We also, in the few places where M68K was also sharing code with these
platforms, define it within the file to CONFIG_SYS_MBAR to match usage.
This should be cleaned up longer term.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>Convert CONFIG_SYS_BR0_PRELIM et al to Kconfig</title>
<updated>2021-12-01T15:58:10Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2021-11-13T23:10:40Z</published>
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<id>urn:sha1:c7fad78ec0ee41b72a58bebb61959570eb937ab1</id>
<content type='text'>
This converts the following to Kconfig:
   CONFIG_SYS_BR0_PRELIM
   CONFIG_SYS_OR1_PRELIM
   CONFIG_SYS_BR1_PRELIM
   CONFIG_SYS_OR2_PRELIM
   CONFIG_SYS_BR2_PRELIM
   CONFIG_SYS_OR2_PRELIM
   CONFIG_SYS_BR3_PRELIM
   CONFIG_SYS_OR3_PRELIM
   CONFIG_SYS_BR4_PRELIM
   CONFIG_SYS_OR4_PRELIM
   CONFIG_SYS_BR5_PRELIM
   CONFIG_SYS_OR5_PRELIM
   CONFIG_SYS_BR6_PRELIM
   CONFIG_SYS_OR6_PRELIM
   CONFIG_SYS_BR7_PRELIM
   CONFIG_SYS_OR7_PRELIM

This also introduces CONFIG_SYS_BR0_PRELIM_BOOL as not all platforms
that can set these values do so.  Add the relevant SYS_BRx_PRELIM_BOOL
to platforms that had not been previously migrated.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>Finish converting CONFIG_SYS_CACHELINE_SIZE to Kconfig</title>
<updated>2021-08-31T21:47:49Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2021-08-26T15:47:59Z</published>
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<id>urn:sha1:ab92b38a0161f0d8efa1c2112d944ef8f755dfbe</id>
<content type='text'>
We move the SYS_CACHE_SHIFT_N options from arch/arm/Kconfig to
arch/Kconfig, and introduce SYS_CACHE_SHIFT_4 to provide a size of 16.
Introduce select statements for other architectures based on current
usage.  For MIPS, we take the existing arch-specific symbol and migrate
to the generic symbol.  This lets us remove a little bit of otherwise
unused code.

Cc: Alexey Brodkin &lt;alexey.brodkin@synopsys.com&gt;
Cc: Anup Patel &lt;anup.patel@wdc.com&gt;
Cc: Atish Patra &lt;atish.patra@wdc.com&gt;
Cc: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Cc: Leo &lt;ycliang@andestech.com&gt;
Cc: Palmer Dabbelt &lt;palmer@dabbelt.com&gt;
Cc: Paul Walmsley &lt;paul.walmsley@sifive.com&gt;
Cc: Sean Anderson &lt;seanga2@gmail.com&gt;
Cc: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
Acked-by: Sean Anderson &lt;seanga2@gmail.com&gt;
Reviewed-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
Reviewed-by: Rick Chen &lt;rick@andestech.com&gt;
</content>
</entry>
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