u-boot.git/arch/powerpc/cpu, branch v2011.03

powerpc/85xx: Handle PCIe initialization requires for P1021 class SoCs

2011-03-29T12:41:37+00:00

The P1011, P1012, P1015, P1016, P1020, P1021, P1024, & P1025 SoCs require
that we initialize the SERDES registers if the lanes are configured for
PCIe.  Additionally these devices PCIe controller do not support ASPM
and we have to explicitly disable it.

Signed-off-by: Prabhakar Kushwaha 
Signed-off-by: Kumar Gala

Merge branch 'master' of git://git.denx.de/u-boot-arm

2011-03-27T19:20:29+00:00

rename _end to __bss_end__

2011-03-27T17:18:37+00:00

Currently, _end is used for end of BSS section.  We want _end to mean
end of u-boot image, so we rename _end to __bss_end__ first.

Signed-off-by: Po-Yu Chuang

powerpc/mpc8xxx: fix workaround for errata DDR111 and DDR134

2011-03-24T14:20:50+00:00

The fix for errata workaround is to avoid covering physical address
0xff000000 to 0xffffffff during the implementation.

Signed-off-by: York Sun 
Signed-off-by: Kumar Gala

powerpc/mpc8xxx: disable rcw_en bit for non-DDR3

2011-03-24T14:20:50+00:00

rcw_en bit is only available for DDR3 controllers. It is a reserved bit on
DDR1 and DDR2 controllers.

Signed-off-by: York Sun 
Signed-off-by: Kumar Gala

powerpc/mpc8xxx: fix recognition of DIMMs with ECC and Address Parity

2011-03-24T14:20:49+00:00

To recognize DIMMs with ECC capability by testing ECC bit only. Not to be
confused by Address Parity bit.

Signed-off-by: York Sun 
Signed-off-by: Kumar Gala

powerpc/85xx: Fix synchronization of timebase on MP boot

2011-03-15T06:25:51+00:00

There is a small ordering issue in the master core in that we need to
make sure the disabling of the timebase in the SoC is visible before we
set the value to 0.  We can simply just read back the value to
synchronizatize the write, before we set TB to 0.

Reported-by: Dan Hettena
Tested-by: Dan Hettena
Signed-off-by: Kumar Gala

mpc8[5/6]xx: Ensure POST word does not get reset

2011-03-13T16:24:44+00:00

The POST word is stored in a spare register in the PIC on MPC8[5/6]xx
processors.  When interrupt_init() is called, this register gets reset
which resulted in all POST_RAM POSTs not being ran due to the corrupted
POST word.  To resolve this, store off POST word before the PIC is
reset, and restore it after the PIC has been initialized.

Signed-off-by: John Schmoller 
Signed-off-by: Peter Tyser 
Signed-off-by: Kumar Gala

powerpc/85xx: Fix plat_mp_up() disabling of BPTR for CoreNet Platforms

2011-03-05T16:16:24+00:00

Copying directly from ECM/PQ3 is not correct for how CoreNet based
platforms handle boot page translation.

Signed-off-by: Ed Swarthout 
Signed-off-by: Kumar Gala

powerpc/mpc8xxx: Fix DDR3 timing_cfg_1 and sdram_mode registers

2011-03-05T16:13:50+00:00

The write recovery time of both registers should match. Since mode register
doesn't support cycles of 9,11,13,15, we should use next higher number for
both registers.

Signed-off-by: York Sun 
Signed-off-by: Kumar Gala