u-boot.git/arch/powerpc/cpu, branch v2011.06 Unnamed repository; edit this file 'description' to name the repository. Minor coding style cleanup. 2011-05-19T20:22:44+00:00 Wolfgang Denk wd@denx.de 2011-05-19T20:21:41+00:00 cd6881b519c94b15907d4f28149e5ed3fd0beea5 Signed-off-by: Wolfgang Denk <wd@denx.de> 
Signed-off-by: Wolfgang Denk <wd@denx.de>
powerpc/mpc8xxx: reword max tCKmin message 2011-05-13T05:36:11+00:00 York Sun yorksun@freescale.com 2011-05-05T23:14:14+00:00 d49f8e04dba056803a80388798b735814b893bbf Reword "The DIMM max tCKmin is ..." to "The DDR clock is faster than the slowest DIMM(s) can support". Fixed interger type in printf as well. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> 
Reword "The DIMM max tCKmin is ..." to "The DDR clock is faster than the slowest
DIMM(s) can support". Fixed interger type in printf as well.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
powerpc/85xx: fix compatible property for the L2 cache node 2011-05-13T05:36:11+00:00 Timur Tabi timur@freescale.com 2011-04-29T23:08:44+00:00 ee4756d4cb9a7a1fccd8601a614740c810722332 The compatible property for the L2 cache node (on 85xx systems that don't have a CPC) was using a value for the property length that did not match the actual length of the property. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> 
The compatible property for the L2 cache node (on 85xx systems that don't
have a CPC) was using a value for the property length that did not match
the actual length of the property.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
PPC405EX CHIP_21 erratum 2011-05-12T14:10:51+00:00 Steven A. Falco sfalco@harris.com 2011-05-05T14:08:35+00:00 644362c40aa8d356d2cc0d230ce0c3bad279c23c APM errata CHIP_21 for the 405EX/EXr (from the rev 1.09 document dated 4/27/11) states that rev D processors may wake up with the wrong feature set. This patch implements the APM-proposed workaround. To enable this patch for your board, add the appropriate define for your CPU to your board header file. See kilauea.h for more information. The following variants are supported: #define CONFIG_SYS_4xx_CHIP_21_405EX_NO_SECURITY #define CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY #define CONFIG_SYS_4xx_CHIP_21_405EXr_NO_SECURITY #define CONFIG_SYS_4xx_CHIP_21_405EXr_SECURITY Please note that if you select the wrong define, your board will not boot, and JTAG will be required to recover. Tested on custom boards using: CONFIG_SYS_4xx_CHIP_21_405EX_NO_SECURITY <sfalco@harris.com> CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY <eibach@gdsys.de> Signed-off-by: Steve Falco <sfalco@harris.com> Acked-by: Dirk Eibach <eibach@gdsys.de> Signed-off-by: Stefan Roese <sr@denx.de> 
APM errata CHIP_21 for the 405EX/EXr (from the rev 1.09 document dated
4/27/11) states that rev D processors may wake up with the wrong feature
set.  This patch implements the APM-proposed workaround.

To enable this patch for your board, add the appropriate define for your
CPU to your board header file.  See kilauea.h for more information.  The
following variants are supported:

#define CONFIG_SYS_4xx_CHIP_21_405EX_NO_SECURITY
#define CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY
#define CONFIG_SYS_4xx_CHIP_21_405EXr_NO_SECURITY
#define CONFIG_SYS_4xx_CHIP_21_405EXr_SECURITY

Please note that if you select the wrong define, your board will not
boot, and JTAG will be required to recover.

Tested on custom boards using:

CONFIG_SYS_4xx_CHIP_21_405EX_NO_SECURITY  <sfalco@harris.com>
CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY     <eibach@gdsys.de>

Signed-off-by: Steve Falco <sfalco@harris.com>
Acked-by: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx 2011-05-10T20:30:07+00:00 Wolfgang Denk wd@denx.de 2011-05-10T20:30:07+00:00 909e9bf3ae6195ac6d52f9e453fba2be8e7e947f 






Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
2011-04-30T20:45:55+00:00

Wolfgang Denk
wd@denx.de

2011-04-30T20:45:55+00:00

aeabdeb7a33c9cff9ae0cd804521d0d691a7c341












mpc832x: add support for the mpc8321 based suvd3 board
2011-04-29T22:44:29+00:00

Heiko Schocher
hs@denx.de

2010-02-18T07:08:25+00:00

62ddcf05e7d7d84498e1387b9b3b9597fe904070

- serial console on UART1
- Ethernet RMII over UCC4
- PHY SMSC LAN8700
- 64MB Flash
- 128 MB DDR2 RAM
- I2C
- bootcount

This board is similiar to the kmeter1 (8360) board,
so common config options are extracted into the
include/configs/km83xx-common.h file.

Signed-off-by: Heiko Schocher <hs@denx.de>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
cc: Kim Phillips <kim.phillips@freescale.com>
cc: Holger Brunck <holger.brunck@keymile.com>
cc: Valentin Longchamp <valentin.longchamp@keymile.com>





- serial console on UART1
- Ethernet RMII over UCC4
- PHY SMSC LAN8700
- 64MB Flash
- 128 MB DDR2 RAM
- I2C
- bootcount

This board is similiar to the kmeter1 (8360) board,
so common config options are extracted into the
include/configs/km83xx-common.h file.

Signed-off-by: Heiko Schocher <hs@denx.de>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
cc: Kim Phillips <kim.phillips@freescale.com>
cc: Holger Brunck <holger.brunck@keymile.com>
cc: Valentin Longchamp <valentin.longchamp@keymile.com>







fsl-ddr: Fix mixed-case macro names
2011-04-29T15:31:01+00:00

Kyle Moffett
Kyle.D.Moffett@boeing.com

2011-04-14T17:39:30+00:00

a2879634c430df3d308f4a3badb37cddca0328f5

Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>





Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>







powerpc/85xx: Change timebase divisor to be defined per processor
2011-04-29T03:09:24+00:00

Kumar Gala
galak@kernel.crashing.org

2011-02-18T11:40:54+00:00

66412c6371cfd6e056679abedea7d6fafe6a0422

Introduce new CONFIG_SYS_FSL_TBCLK_DIV on 85xx platforms because
different SoCs have different divisor amounts.  All the PQ3 parts are
/8, the P4080/P4080 is /16, and P2040/P3041/P5020 are /32.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>





Introduce new CONFIG_SYS_FSL_TBCLK_DIV on 85xx platforms because
different SoCs have different divisor amounts.  All the PQ3 parts are
/8, the P4080/P4080 is /16, and P2040/P3041/P5020 are /32.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>







powerpc/85xx: Implement work-around for P4080 erratum SERDES-A001
2011-04-29T03:09:23+00:00

Timur Tabi
timur@freescale.com

2011-04-18T22:16:00+00:00

d90fdba6ca0b08c77cced6e914609e3696dd5909

Bank powerdown through RCW[SRDS_LPD_Bn] for XAUI on FM2 and SGMII on FM1
are swapped.

Erratum SERDES-A001 says that if bank two is kept disabled and after bank
three is enabled, then the PLL for bank three won't lock properly.  The
work-around is to enable and then disable bank two after bank three is
enabled.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>





Bank powerdown through RCW[SRDS_LPD_Bn] for XAUI on FM2 and SGMII on FM1
are swapped.

Erratum SERDES-A001 says that if bank two is kept disabled and after bank
three is enabled, then the PLL for bank three won't lock properly.  The
work-around is to enable and then disable bank two after bank three is
enabled.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>