u-boot.git/arch/powerpc/cpu, branch v2012.07

MPC83xx, MPC85xx: compile stub cache function

2012-07-21T21:37:48+00:00

An empty flush_dcache_range() was added into MPC83xx and MPC85xx to
work with drivers shared with other architecture.  However, it is
compiled only if USB is set, but it is required for other drivers
(FSL_ESDHC), too.

Signed-off-by: Stefano Babic 
CC: Andy Fleming 
CC: Dirk Behme 
CC: Marek Vasut 
CC: Wolfgang Denk 

Added MPC83xx version.

Signed-off-by: Wolfgang Denk

Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

2012-07-08T17:16:14+00:00

* 'master' of git://git.denx.de/u-boot-mpc85xx:
  powerpc/mpc85xx: Fix Handling the lack of L2 cache on P2040/P2040E
  powerpc/mpc85xx: Workaround for erratum CPU_A011
  powerpc/mpc85xx: Ignore E bit for SVR_SOC_VER()
  powerpc/P4080: Check SVR for CPU22 workaround
  lib/powerpc: addrmap_phys_to_virt() should return a pointer
  powerpc/85xx: clean up P1022DS board configuration header file
  powerpc/85xx: fdt_set_phy_handle() should return an error code
  powerpc/85xx: minor clean-ups to the P2020DS board header file
  powerpc/p1010rdb: add readme document for p1010rdb
  powerpc/mpc85xx:NAND_SPL:Avoid IFC/eLBC Base address setting
  powerpc/mpc85xx:Add debugger support for e500v2 SoC
  powerpc/85xx:Fix NAND code base to support debugger
  powerpc/85xx:Make debug exception vector accessible
  powerpc/85xx:Fix MSR[DE] bit in MSR to support debugger
  PATCH 1/4][v4] doc:Add documentation for e500 external debugger support
  powerpc/p1010rdb: update mux config of p1010rdb board
  powerpc/mpc85xx:Add BSC9131 RDB Support
  powerpc/mpc85xx:Add BSC9131/BSC9130/BSC9231 Processor Support
  powerpc/85xx: Add USB device-tree fixup for various platforms

Signed-off-by: Wolfgang Denk

powerpc/mpc85xx: Fix Handling the lack of L2 cache on P2040/P2040E

2012-07-06T22:30:33+00:00

Fix SVR checking for commit acf3f8da.

Signed-off-by: York Sun

powerpc/mpc85xx: Workaround for erratum CPU_A011

2012-07-06T22:30:33+00:00

Erratum NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in rev 3.0.
It also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1. It shares the
same workaround as erratum CPU22. Rearrange registers usage in assembly
code to avoid accidental overwriting.

Signed-off-by: York Sun

powerpc/mpc85xx: Ignore E bit for SVR_SOC_VER()

2012-07-06T22:30:33+00:00

We don't care E bit of SVR in most cases. Clear E bit for SVR_SOC_VER().
This will simplify the coding. Use IS_E_PROCESSOR() to identify SoC with
encryption. Remove all _E entries from SVR list and CPU list.

Signed-off-by: York Sun

powerpc/P4080: Check SVR for CPU22 workaround

2012-07-06T22:30:33+00:00

Workaround for erratum CPU22 applies to P4080 rev 1 and rev 2 only.

Signed-off-by: York Sun

powerpc/mpc85xx:NAND_SPL:Avoid IFC/eLBC Base address setting

2012-07-06T22:30:31+00:00

During NAND_SPL boot, base address and different register are programmed
default by corresponding NAND controllers(eLBC/IFC). These settings are
sufficient enough for NAND SPL.

Avoid updating these register.They will be programmed during NAND RAMBOOT.

Signed-off-by: Prabhakar Kushwaha

powerpc/85xx:Fix NAND code base to support debugger

2012-07-06T22:30:30+00:00

Update NAND code base to ovecome e500 and e500v2's second limitation i.e. IVPR
+ IVOR15 should be valid fetchable OP code address.

As NAND SPL does not compile vector table so making sure IVOR + IVOR15 points to
any fetchable valid data

Signed-off-by: Radu Lazarescu 
Signed-off-by: Marius Grigoras 
Signed-off-by: Prabhakar Kushwaha

powerpc/85xx:Make debug exception vector accessible

2012-07-06T22:30:30+00:00

Debugging of e500 and e500v1 processer requires debug exception vecter (IVPR +
IVOR15) to have valid and fetchable OP code.

1) While executing in translated space (AS=1), whenever a debug exception is
generated, the MSR[DS/IS] gets cleared i.e. AS=0 and the processor tries to
fetch an instruction from the debug exception vector (IVPR + IVOR15); since now
we are in AS=0, the application needs to ensure the proper TLB configuration to
have (IVOR + IVOR15) accessible from AS=0 also.
Create a temporary TLB in AS0 to make sure debug exception verctor is
accessible on debug exception.

2) Just after relocation in DDR, Make sure IVPR + IVOR15 points to valid opcode

Signed-off-by: Radu Lazarescu 
Signed-off-by: Marius Grigoras 
Signed-off-by: Prabhakar Kushwaha

powerpc/85xx:Fix MSR[DE] bit in MSR to support debugger

2012-07-06T22:30:30+00:00

Debugging of e500 and e500v1 processer requires MSR[DE] bit to be set always.
Where MSR = Machine State register

Make sure of MSR[DE] bit is set uniformaly across the different execution
address space i.e. AS0 and AS1.

Signed-off-by: Radu Lazarescu 
Signed-off-by: Catalin Udma 
Signed-off-by: Marius Grigoras 
Signed-off-by: Prabhakar Kushwaha