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<title>u-boot.git/arch/powerpc/cpu, branch v2013.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/powerpc/cpu?h=v2013.01</id>
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<updated>2012-12-13T18:46:55Z</updated>
<entry>
<title>env: Use getenv_yesno() more generally</title>
<updated>2012-12-13T18:46:55Z</updated>
<author>
<name>Joe Hershberger</name>
<email>joe.hershberger@ni.com</email>
</author>
<published>2012-12-12T04:16:22Z</published>
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<id>urn:sha1:ec8a252cd492a7a409d6912aebeff34bb9e1e1e1</id>
<content type='text'>
Move the getenv_yesno() to env_common.c and change most checks for
'y' or 'n' to use this helper.

Signed-off-by: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
</content>
</entry>
<entry>
<title>mpc5200: Add SPL support</title>
<updated>2012-12-05T16:30:51Z</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2012-08-16T15:53:18Z</published>
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<id>urn:sha1:083f2e08d2265a096a1ab52d43b4abb8e069977d</id>
<content type='text'>
This patch adds SPL booting support (NOR flash) for the
MPC5200 platforms.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>powerpc: Extract EPAPR_MAGIC constants into processor.h</title>
<updated>2012-12-05T16:27:02Z</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2012-08-23T07:25:37Z</published>
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<id>urn:sha1:966b11c74909d2c1b38070dc4ab5708fba5be43d</id>
<content type='text'>
By extracting these defines into a header, they can be re-used by other
C sources as well. This will be done by the SPL framework OS boot
support.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>powerpc/mpc85xx: Fix a bug introduced by CONFIG_PPC_SPINTABLE_COMPATIBLE</title>
<updated>2012-11-28T00:28:08Z</updated>
<author>
<name>York Sun</name>
<email>yorksun@freescale.com</email>
</author>
<published>2012-11-08T12:33:39Z</published>
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<id>urn:sha1:afbfdf545090472b734367ac2c874bfbe8928790</id>
<content type='text'>
Fix a bug introduced by this patch
powerpc/mpc85xx: Temporary fix for spin table backward compatibility

Should have checked both CONFIG_PPC_SPINTABLE_COMPATIBLE and CONFIG_MP in
cpu_init.c.

Signed-off-by: York Sun &lt;yorksun@freescale.com&gt;
Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
</content>
</entry>
<entry>
<title>powerpc/85xx: update the work-around for P4080 erratum SERDES-9</title>
<updated>2012-11-28T00:28:07Z</updated>
<author>
<name>Timur Tabi</name>
<email>timur@freescale.com</email>
</author>
<published>2012-11-01T08:20:22Z</published>
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<id>urn:sha1:b25f6de7c03cfa8663439581c90d303588168a29</id>
<content type='text'>
The documented work-around for P4080 erratum SERDES-9 has been updated.
It is now compatible with the work-around for erratum A-4580.

This requires adding a few bitfield macros for the BnTTLCRy0 register.

Signed-off-by: Timur Tabi &lt;timur@freescale.com&gt;
Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
</content>
</entry>
<entry>
<title>powerpc/p4080ds: fix PCI-e x8 link training down failure</title>
<updated>2012-11-28T00:28:07Z</updated>
<author>
<name>Yuanquan Chen</name>
<email>B41889@freescale.com</email>
</author>
<published>2012-11-26T23:49:45Z</published>
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<id>urn:sha1:c0a4e6b889a702cc2c8375619ce7b093f6b3b1de</id>
<content type='text'>
Due to SerDes configuration error, if we set the PCI-e controller link width
as x8 in RCW and add a narrower width(such as x4, x2 or x1) PCI-e device to
PCI-e slot, it fails to train down to the PCI-e device's link width. According
to p4080ds errata PCIe-A003, we reset the PCI-e controller link width to x4 in
u-boot. Then it can train down to x2 or x1 width to make the PCI-e link between
RC and EP.

Signed-off-by: Yuanquan Chen &lt;B41889@freescale.com&gt;
Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
</content>
</entry>
<entry>
<title>powerpc/85xx: implement check for erratum A-004580 work-around</title>
<updated>2012-11-28T00:28:07Z</updated>
<author>
<name>Timur Tabi</name>
<email>timur@freescale.com</email>
</author>
<published>2012-11-01T08:20:23Z</published>
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<id>urn:sha1:d607b9684b188d020a00e9cfaa502b782f29d538</id>
<content type='text'>
The work-around for erratum A-004580 ("Internal tracking loop can falsely
lock causing unrecoverable bit errors") is implemented via the PBI
(pre-boot initialization code, typically attached to the RCW binary).
This is because the work-around is easier to implement in PBI than in
U-Boot itself.

It is still useful, however, for the 'errata' command to tell us whether
the work-around has been applied.  For A-004580, we can do this by verifying
that the values in the specific registers that the work-around says to
update.

This change requires access to the SerDes lane sub-structure in
serdes_corenet_t, so we make it a named struct.

Signed-off-by: Timur Tabi &lt;timur@freescale.com&gt;
Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
</content>
</entry>
<entry>
<title>powerpc/mpc8xxx: take fdt_fixup_crypto_node() off the checkstack list</title>
<updated>2012-11-28T00:28:07Z</updated>
<author>
<name>Kim Phillips</name>
<email>kim.phillips@freescale.com</email>
</author>
<published>2012-10-31T11:09:26Z</published>
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<id>urn:sha1:345d6efdc713334387bf07cd0c122b3b03d401b2</id>
<content type='text'>
by moving compat_strlist into the .bss section.

0xfe004d80 fdt_fixup_crypto_node [u-boot]:		264

Signed-off-by: Kim Phillips &lt;kim.phillips@freescale.com&gt;
Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
</content>
</entry>
<entry>
<title>powerpc/mpc85xx: Temporary fix for spin table backward compatibility</title>
<updated>2012-11-28T00:28:06Z</updated>
<author>
<name>York Sun</name>
<email>yorksun@freescale.com</email>
</author>
<published>2012-10-28T08:12:54Z</published>
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<id>urn:sha1:2a5fcb835f6e976ed0eb34c413d40f2d4a5e8d1f</id>
<content type='text'>
Once u-boot sets the spin table to cache-enabled memory, old kernel which
uses cache-inhibit mapping without coherence will not work properly. We
use this temporary fix until kernel has updated its spin table code.
For now this fix is activated by default. To disable this fix for new
kernel, set environmental variable "spin_table_compat=no". After kernel
has updated spin table code, this default shall be changed.

Signed-off-by: York Sun &lt;yorksun@freescale.com&gt;
Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
</content>
</entry>
<entry>
<title>powerpc/85xx: implement check for erratum A-004849 work-around</title>
<updated>2012-11-28T00:28:06Z</updated>
<author>
<name>Timur Tabi</name>
<email>timur@freescale.com</email>
</author>
<published>2012-10-25T12:40:00Z</published>
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<id>urn:sha1:0118033b6700fc96a84a8c0593af3cbe2f10a6dc</id>
<content type='text'>
The work-around for erratum A-004849 ("CoreNet fabric (CCF) can exhibit a
deadlock under certain traffic patterns causing the system to hang") is
implemented via the PBI (pre-boot initialization code, typically attached
to the RCW binary).  This is because the work-around is easier to implement
in PBI than in U-Boot itself.

It is still useful, however, for the 'errata' command to tell us whether
the work-around has been applied.  For A-004849, we can do this by verifying
that the values in the specific registers that the work-around says to
update.

Signed-off-by: Timur Tabi &lt;timur@freescale.com&gt;
Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
</content>
</entry>
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