u-boot.git/arch/powerpc/cpu, branch v2013.07

powerpc/mpc85xx:Disable Debug TLB entry for non-minimal SPL

2013-07-16T22:44:30Z

CONFIG_SPL_BUILD creates debug TLB entry, so disable it before init_tlbs. CONFIG_SPL_INIT_MINIMAL never creates any debug TLB entry, so no need of disable_tlb(). Signed-off-by: Prabhakar Kushwaha Signed-off-by: Andy Fleming

powerpc/85xx: Add P1023RDB board support

2013-06-20T22:08:53Z

P1023RDB Specification: ----------------------- Memory subsystem: 512MB DDR3 (Fixed DDR on board) 64MB NOR flash 128MB NAND flash Ethernet: eTSEC1: Connected to Atheros AR8035 GETH PHY eTSEC2: Connected to Atheros AR8035 GETH PHY PCIe: Three mini-PCIe slots USB: Two USB2.0 Type A ports I2C: AT24C08 8K Board EEPROM (8 bit address) Signed-off-by: Chunhe Lan Cc: Scott Wood Signed-off-by: Andy Fleming

powerpc/mpc85xx:Disable Debug TLB entry before init_tlbs

2013-06-20T22:08:53Z

init_tlbs() initialize all the TLB entries required for the system. So disable DEBUG TLB entry before TLB entries initialization. Signed-off-by: Prabhakar Kushwaha Signed-off-by: Andy Fleming

powerpc: mpc85xx/mpc86xx: Fix off-by-one boundary checking with ARRAY_SIZE

2013-06-20T22:08:51Z

If a variable is used as array subscript, it's valid value range is 0 ... ARRAY_SIZE -1. Signed-off-by: Axel Lin Signed-off-by: Andy Fleming

powerpc/mpc85xx: modify the functionality clear_bss and aligning the end address of the BSS

2013-06-20T22:08:50Z

There will clear the BSS in the function clear_bss(), the reset address of the BSS started from the __bss_start, and increased by four-byte increments, finally stoped depending on the address is equal to the _bss_end. If the end address __bss_end is not alignment to 4byte, it will be an infinite loop. 1. The reset action stoped depending on the reset address is greater than or equal the end address of the BSS. 2. The end address of the BSS should be 4byte aligned. Because the reset unit is 4 Bytes. This patch is on top of the patch "powerpc/mpc85xx: support application without resetvec segment in the linker script". Signed-off-by: Ying Zhang Signed-off-by: Andy Fleming

powerpc/mpc85xx: support application without resetvec segment in the linker script

2013-06-20T22:08:50Z

For SD/SPI 2-stage bootloader, the On-Chip Rom code loads the SPL into L2 SRAM, then jump to it to begin execution. After that, the SPL loads the final uboot image into DDR, then jump to it to begin execution. The segment .resetvec in the SPL and in final U-boot is useless. So, add new symbols CONFIG_SYS_MPC85XX_NO_RESETVEC for this application. If CONFIG_SYS_MPC85XX_NO_RESETVEC is set, the segment .resetvec is excluded and the segment .bootpg is placed in the previous 4K of the segment .text. Signed-off-by: Ying Zhang Signed-off-by: Andy Fleming

powerpc/mpc85xx: work around erratum A-006593

2013-06-20T22:08:49Z

Erratum A-006593 is "Atomic store may report failure but still allow the store data to be visible". The workaround is: "Set CoreNet Platform Cache register CPCHDBCR0 bit 21 to 1'b1. This may have a small impact on synthetic write bandwidth benchmarks but should have a negligible impact on real code." Signed-off-by: Scott Wood Signed-off-by: Andy Fleming

fsl_ifc: add support for different IFC bank count

2013-06-20T22:08:49Z

Calculate reserved fields according to IFC bank count 1. Move csor_ext register behind csor register and fix res offset 2. Move ifc bank count to config_mpc85xx.h to support 8 bank count 3. Guard fsl_ifc.h with CONFIG_FSL_IFC macro to eliminate the compile error on some devices that does not have IFC controller. Signed-off-by: Mingkai Hu Signed-off-by: Andy Fleming

powerpc/boot: Change the macro of Boot from SRIO and PCIE master module

2013-06-20T22:08:48Z

Currently, the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" can enable the master module of Boot from SRIO and PCIE on a platform. But this is not a silicon feature, it's just a specific booting mode based on the SRIO and PCIE interfaces. So it's inappropriate to put the macro into the file arch/powerpc/include/asm/config_mpc85xx.h. Change the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" to "CONFIG_SRIO_PCIE_BOOT_MASTER", remove them from arch/powerpc/include/asm/config_mpc85xx.h file, and add those macros in configuration header file of each board which can support the master module of Boot from SRIO and PCIE. Signed-off-by: Liu Gang Signed-off-by: Andy Fleming

powerpc: Use lower case for the core names

2013-06-20T21:09:09Z

Freescale documentation presents the PowerPC core names in lower case, such as "e300", "e500", "e600", etc. Change the upper case occurrences into lower case so that the core names reported in U-boot can match the ones from the documentation. While at it also fix a checkpatch error: ERROR: space prohibited before that close parenthesis ')' #53: FILE: arch/powerpc/cpu/mpc86xx/cpu.c:81: + printf("e600 Core %d", (msscr0 & 0x20) ? 1 : 0 ); Reported-by: Heinz Wrobel Signed-off-by: Fabio Estevam Signed-off-by: Andy Fleming