u-boot.git/arch/powerpc/cpu, branch v2014.07

blackfin, powerpc: remove redundant definitions of ARRAY_SIZE

2014-07-07T23:47:12Z

Since ARRAY_SIZE macro is defined in include/common.h, re-defining it in arch-specific files is redundant. Signed-off-by: Masahiro Yamada Acked-by: Stefan Roese Acked-by: Sonic Zhang

mpc8xx: remove spc1920 board support

2014-07-07T23:43:02Z

This board is old enough and has no maintainer. Signed-off-by: Masahiro Yamada

mpc8xx: remove fads board support

2014-07-07T23:43:02Z

These boards are old enough and have no maintainers. Signed-off-by: Masahiro Yamada

mpc8xx: remove netta, netta2, netphone board support

2014-07-07T23:43:02Z

These boards are old enough and have no maintainers. Signed-off-by: Masahiro Yamada

mpc8xx: remove RPXlite_dw, quantum board support

2014-07-07T23:43:01Z

These boards are old enough and have no maintainers. Signed-off-by: Masahiro Yamada

mpc8xx: remove qs850, qs860t board support

2014-07-07T23:43:01Z

These boards are old enough and have no maintainers. Signed-off-by: Masahiro Yamada

Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

2014-06-05T21:38:30Z

nand_spl: remove nand_spl infrastructure

2014-06-05T21:01:59Z

Remove the common infrastructure of nand_spl and clean-up the code inside ifdef(CONFIG_NAND_U_BOOT)..endif. Signed-off-by: Masahiro Yamada

powerpc/mpc85xx: Add workaround to enable TDM on T1040

2014-06-05T20:45:07Z

This is a workaround for 32 bit hardware limitation of TDM. T1040 has 36 bit physical addressing, TDM DMAC register are 32 bit wide but need to store address of CCSR space which lies beyond 32 bit address range. This workaround creats a LAW to enable access of TDM DMA to CCSR by mapping CCSR to overlap with DDR. A hole of 16M is created in memory using device tree. This workaround law is set only if "tdm" is defined in hwconfig. Also disable POST tests and add LIODN for TDM Signed-off-by: Sandeep Singh Reviewed-by: York Sun

powerpc/serdes: Add the workaround for erratum A-007186

2014-06-05T20:45:07Z

SerDes PLL is calibrated at reset. When the junction temperature delta from the time the PLL is calibrated exceeds +56C/-66C, jitter may increase and can cause PLL to unlock. This workaround overwrite the SerDes registers with new values, to calibrate SerDes registers. These values are known to work fine for all temperature ranges. This workaround is valid for B4, T4 and T2 platforms, so added in their config. Signed-off-by: Shaveta Leekha Signed-off-by: Poonam Aggrwal [York Sun: replaced typedef ccsr_sfp_regs_t with struct ccsr_sfp_regs] Reviewed-by: York Sun