u-boot.git/arch/powerpc/cpu, branch v2016.07 Unnamed repository; edit this file 'description' to name the repository. powerpc: mpc85xx: Do not build errata command in SPL 2016-07-05T15:40:28+00:00 Marek Vasut marex@denx.de 2016-07-05T15:40:27+00:00 12c67d7522d77c5aa5ee1e5ec4147b569ccb7666 The errata command is useless in SPL, so don't build it. This fixes multiple build failures on PowerPC. Signed-off-by: Marek Vasut <marex@denx.de> Cc: York Sun <york.sun@nxp.com> Fixes: 92623672f9d3 ("fsl: usb: make errata function common for PPC and ARM") 
The errata command is useless in SPL, so don't build it. This fixes
multiple build failures on PowerPC.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: York Sun <york.sun@nxp.com>
Fixes: 92623672f9d3 ("fsl: usb: make errata function common for PPC and ARM")
arch/powerpc: Simplify some calculations using ARRAY_SIZE() macro. 2016-06-04T05:13:12+00:00 Robert P. J. Day rpjday@crashcourse.ca 2016-05-23T10:49:21+00:00 b7707b043ebbf88fe0fb49442db9316ded3a0740 Replace a number of array length calculations with the ARRAY_SIZE() macro, for clarity. Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca> Reviewed-by: York Sun <york.sun@nxp.com> 
Replace a number of array length calculations with the ARRAY_SIZE()
macro, for clarity.

Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
Reviewed-by: York Sun <york.sun@nxp.com>
Delete tests of CONFIG_OF_LIBFDT when testing CONFIG_OF_BOARD_SETUP 2016-05-27T19:41:16+00:00 Robert P. J. Day rpjday@crashcourse.ca 2016-05-19T19:23:12+00:00 7ffe3cd62e5af2cda1e18c6d896cab58bfb0c811 Since CONFIG_OF_BOARD_SETUP depends on CONFIG_OF_LIBFDT: config OF_BOARD_SETUP bool "Set up board-specific details in device tree before boot" depends on OF_LIBFDT ... remove superfluous tests of CONFIG_OF_LIBFDT when testing for CONFIG_OF_BOARD_SETUP. Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca> [trini: Typo fix: s/ifdefi/ifdef/] Signed-off-by: Tom Rini <trini@konsulko.com> 
Since CONFIG_OF_BOARD_SETUP depends on CONFIG_OF_LIBFDT:

  config OF_BOARD_SETUP
          bool "Set up board-specific details in device tree before boot"
          depends on OF_LIBFDT
          ...

remove superfluous tests of CONFIG_OF_LIBFDT when testing for
CONFIG_OF_BOARD_SETUP.

Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
[trini: Typo fix: s/ifdefi/ifdef/]
Signed-off-by: Tom Rini <trini@konsulko.com>
powerpc: Drop unused code related to generic board 2016-05-27T19:39:54+00:00 Simon Glass sjg@chromium.org 2016-05-15T00:49:34+00:00 14c67ebaefec6d477603454aa2998c36da40453b Since generic board init is enabled, this is not used. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> 
Since generic board init is enabled, this is not used. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2016-05-25T11:19:31+00:00 Tom Rini trini@konsulko.com 2016-05-25T11:19:31+00:00 826d06dbdd0e29ab0d8bd76d1ca640e2dfdb076c 






powerpc/mpc85xx: set L2PE in L2CSR0 before enabling L2 cache
2016-05-24T17:31:21+00:00

Aneesh Bansal
aneesh.bansal@nxp.com

2016-04-18T17:28:33+00:00

82eda68444fa4d026bcf1f59c7c0d044ddbcb193

While enabling L2 cache, the value of L2PE (L2 cache parity/ECC
error checking enable) must not be changed while the L2 cache is
enabled.
So, L2PE must be set before enabling L2 cache.

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>





While enabling L2 cache, the value of L2PE (L2 cache parity/ECC
error checking enable) must not be changed while the L2 cache is
enabled.
So, L2PE must be set before enabling L2 cache.

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>







crypto/fsl: add support for multiple SEC engines initialization
2016-05-18T15:51:46+00:00

Alex Porosanu
alexandru.porosanu@freescale.com

2016-04-29T12:18:00+00:00

76394c9c9139b82e21a6e52da0e7341a3374f4be

For SoCs that contain multiple SEC engines, each of them needs
to be initialized (by means of initializing among others the
random number generator).

Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>





For SoCs that contain multiple SEC engines, each of them needs
to be initialized (by means of initializing among others the
random number generator).

Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>







Fix various typos, scattered over the code.
2016-05-06T01:39:26+00:00

Robert P. J. Day
rpjday@crashcourse.ca

2016-05-04T08:47:31+00:00

1cc0a9f49657734c54939f03fc1e3ca0ec9d7eef

Spelling corrections for (among other things):

* environment
* override
* variable
* ftd (should be "fdt", for flattened device tree)
* embedded
* FTDI
* emulation
* controller





Spelling corrections for (among other things):

* environment
* override
* variable
* ftd (should be "fdt", for flattened device tree)
* embedded
* FTDI
* emulation
* controller







powerpc: mpc85xx: Enable pre-relocation malloc for MPC85xx
2016-04-08T22:42:10+00:00

mario.six@gdsys.cc
mario.six@gdsys.cc

2016-04-05T13:05:37+00:00

50689461205e0125759eb1a43787383a3fa09b48

To enable DM on MPC85xx, we need pre-relocation malloc, which is
implemented in this patch.

We also make sure that the IVORs are always 4-aligned on e500 to prevent
alignment exceptions caused by code changes in start.S.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Cc: York Sun <york.sun@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>





To enable DM on MPC85xx, we need pre-relocation malloc, which is
implemented in this patch.

We also make sure that the IVORs are always 4-aligned on e500 to prevent
alignment exceptions caused by code changes in start.S.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Cc: York Sun <york.sun@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>







usb: Rename ehci-fsl.h to ehci-ci.h
2016-04-01T21:18:10+00:00

Mateusz Kulikowski
mateusz.kulikowski@gmail.com

2016-03-31T21:12:23+00:00

e162c6b1a758c6bda26417c1075fef7a97fb6743

Most of ehci-fsl header describe USB controller
designed by Chipidea and used by various SoC vendors.

This patch renames it to a generic header: ehci-ci.h
Contents of file are not changed (so it contains several
references to freescale SoCs).

Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
Tested-by: Simon Glass <sjg@chromium.org>





Most of ehci-fsl header describe USB controller
designed by Chipidea and used by various SoC vendors.

This patch renames it to a generic header: ehci-ci.h
Contents of file are not changed (so it contains several
references to freescale SoCs).

Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
Tested-by: Simon Glass <sjg@chromium.org>