u-boot.git/arch/powerpc/cpu, branch v2017.03

Merge git://git.denx.de/u-boot-fsl-qoriq

2017-02-04T01:33:42Z

Signed-off-by: Tom Rini Conflicts: configs/ls1046aqds_defconfig configs/ls1046aqds_nand_defconfig configs/ls1046aqds_qspi_defconfig configs/ls1046aqds_sdcard_ifc_defconfig configs/ls1046aqds_sdcard_qspi_defconfig configs/ls1046ardb_emmc_defconfig configs/ls1046ardb_qspi_defconfig configs/ls1046ardb_sdcard_defconfig

arch: powerpc: update the eLBC IP input clock

2017-02-03T22:31:45Z

eLBC IP clock is always a constant divisor of platform clock pre-defined per SoC. Clock ratio register (LCRR) used in current implementation governs eLBC IP output cloc. Update sys_info->freq_localbus to represent eLBC input clock with value constant divisor of platform clock. Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun

arch: powerpc: Move CONFIG_FSL_ELBC to Kconfig

2017-02-03T22:31:25Z

Enable ELBC from Kconfig. Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun

arch: powerpc: update the IFC IP input clock

2017-02-03T22:31:11Z

IFC IP clock is always a constant divisor of platform clock pre-defined per SoC. Clock control register (CCR) used in current implementation governs IFC IP output clock. Update sys_info->freq_localbus to represent IFC input clock with value constant divisor of platform clock. Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun

arch: powerpc: Move CONFIG_FSL_IFC to Kconfig

2017-02-03T22:31:02Z

Enable IFC from Kconfig. Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun

powerpc: mpc85xx: Use symbolic names for cache control bits

2017-02-01T01:51:34Z

We should use the symbolic names for the cache control bits. Signed-off-by: Mark Marshall Reviewed-by: Thomas Graziadei Reviewed-by: York Sun

powerpc: mpc83xx: Enable pre-relocation malloc

2017-02-01T01:50:35Z

To enable DM on MPC83xx, we need pre-relocation malloc, which is implemented in this patch. Signed-off-by: Mario Six [York S: Fixed compiling warning for unused variable 'i'] Reviewed-by: York Sun

powerpc: mpc83xx: Minimize r1 modification

2017-01-31T17:35:06Z

The r1 register is modified several times during the cache-ram setup of the MPC83xx SoCs. Since this SP modification confuses debuggers, we use a general purpose register to compute the new stack pointer value, and only set the SP once after all computations are done. Signed-off-by: Mario Six Reviewed-by: Joakim Tjernlund Reviewed-by: York Sun

Merge git://git.denx.de/u-boot-mpc85xx

2017-01-25T22:38:45Z

Drop prt_mpc5xxx_clks() in favour of print_cpuinfo()

2017-01-25T22:38:44Z

Rather than having an arch-specific function, use the existing generic one. Signed-off-by: Simon Glass