u-boot.git/arch/powerpc/cpu, branch v2023.07

Merge branch 'for-2023.07-2' of https://source.denx.de/u-boot/custodians/u-boot-mpc8xx

2023-05-07T13:44:27Z

This pull request adds misc fixes for cssi boards and activates CPM relocation in order to enable the use of SCC4 in QMC (QUICC Multi-Channel) mode.

powerpc: mpc8xx: Add SMC relocation CPM microcode

2023-05-05T05:26:53Z

In order to use QMC mode in the CPM, a SCC requires more space in parameter RAM. After SCC1 there is I2C parameter RAM and after SCC2 there is SPI parameter RAM. MPC866 and MPC885 can already relocate I2C and. SPI parameter RAM. But in order to free space after SCC3 and SCC4, SMC1 and SMC2 need to be relocated. In order to do so, a CPM microcode patch is required. Binary data for that patch is copied from Linux kernel. Signed-off-by: Christophe Leroy

powerpc: mpc885: Add CPM USB-SOF microcode for CPM15 ERRATA

2023-05-05T05:26:53Z

MPC885 CPU has the following ERRATA: When the USB controller is configured in Host mode, and the SOF generation (SFTE=1 in USMOD register) is being used, there may be false CRC error indication in other SCCs. Although the data is received correctly, the CRC result will be corrupted. Add capability to load the related microcode to fix it. The microcode binary data is copied from Linux kernel. Other microcode will be added in following patch so make it a Kconfig choice. Signed-off-by: Christophe Leroy

powerpc: mpc8xx: Reorganise init RAM

2023-05-04T10:40:47Z

Using SMC relocation microcode patch or USB-SOF microcode patch will disable DPRAM memory from 0x2000 to 0x2400 and from 0x2f00 to 0x3000. At the time being, init RAM is setup to use 0x2800-0x2e00, but the stack pointer goes beyond 0x2800 and even beyond 0x2400. For the time being we are not going to use any microcode patch that uses memory about 0x3000, so reorganise setup to use: - 0x2800 - 0x2e00 for init malloc and global data and CPM buffers - 0x3000 - 0x3c00 for init stack For more details about CPM dual port ram, see commit b1d62424cb ("powerpc: mpc8xx: redistribute data in CPM dpram") Signed-off-by: Christophe Leroy

powerpc: mpc8xx: CPM parameter RAM can be anywhere

2023-05-04T08:58:07Z

With relocation, CPM parameter RAM can be anywhere in the dual port RAM, so don't split dual port RAM. Remove dparam and dparam16 members of struct comm_proc PROFF_XXX become offsets from the start of dual port RAM, then they are now consistant with the offsets in RPBASE registers. Signed-off-by: Christophe Leroy

mpc83xx: Don't allow W and G bits in IBATs

2023-05-01T22:59:33Z

The "Programming Environments Manual for 32-Bit Implementations of the PowerPC™ Architecture" says "W and G bits are not defined for IBAT registers. Attempting to write to these bits causes boundedly-undefined results" The "e300 Power Architecture™ Core Family Reference Manual" says the same: "Neither the W or G bits of the IBAT registers should be set. Attempting to write to these bits causes boundedly-undefined results." Remove the possibility to set those bytes. Fixes: 30915ab95d9 ("mpc83xx: Migrate BATS config to Kconfig") Signed-off-by: Christophe Leroy Cc: Mario Six

board: cssi: Add CPU board CMPCPRO

2023-04-28T15:52:23Z

CSSI has another CPU board, similar to the CMPC885 board that get plugged on the two base boards MCR3000_2G and MIAE. That CPU board is called CMPCPRO because it has a MPC8321E CPU, also known as Power QUICC II PRO. Signed-off-by: Christophe Leroy

powerpc: mpc83xx: Don't activate MMU when not necessary

2023-04-06T12:50:03Z

At startup, some RAM is needed (for instance for stack) before DRAM is initialised. One way to offer such RAM, used by mpc83xx, is to lock some entries in the cache. To do that, MMU needs to be activated. On mpc83xx having a QUICC Engine an alternative is to user some part of from the Multi User RAM, like done on mpc8xx for instance. For that, the MMU is not needed. Activating the MMU is problematic because exception vectors are not setup yet so in case of ISI or DSI that CPU will crash and reboot. At the time being, MMU is activated regardless. Only activate it when locking cache entries to provide initial RAM. Signed-off-by: Christophe Leroy

powerpc: mpc832x: Fix reset word

2023-04-06T12:50:03Z

According to the reference manual, the Reset Configuration Word Low Register bits 2-3 must be set to 0b10. Signed-off-by: Christophe Leroy

watchdog: mpc8xxx: Add support for mpc83xx

2023-04-06T12:50:03Z

Introduce a new compatible "fsl,pq2pro-wdt" On mpc83xx, the prescaling factor is 0x10000. Don't write the watchdog configuration register in start.S as it can be written only once. Signed-off-by: Christophe Leroy