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<title>u-boot.git/arch/powerpc/include/asm/fsl_errata.h, branch master</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/powerpc/include/asm/fsl_errata.h?h=master</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/arch/powerpc/include/asm/fsl_errata.h?h=master'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<updated>2015-12-14T02:27:28Z</updated>
<entry>
<title>fsl/errata: move fsl_errata.h to common directory</title>
<updated>2015-12-14T02:27:28Z</updated>
<author>
<name>Shengzhou Liu</name>
<email>Shengzhou.Liu@freescale.com</email>
</author>
<published>2015-11-20T07:52:03Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=a07bdad749ea080e009a82ba40e791dc7361ab54'/>
<id>urn:sha1:a07bdad749ea080e009a82ba40e791dc7361ab54</id>
<content type='text'>
move arch/powerpc/include/asm/fsl_errata.h to include/fsl_errata.h
to make it public for both ARM and POWER SoCs.

Signed-off-by: Shengzhou Liu &lt;Shengzhou.Liu@freescale.com&gt;
[York Sun: fix soc.h path in fsl_errata.h]
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
<entry>
<title>powerpc/t2080: enable erratum_a007186 for t2080 rev1.1</title>
<updated>2015-04-20T17:15:29Z</updated>
<author>
<name>Shengzhou Liu</name>
<email>Shengzhou.Liu@freescale.com</email>
</author>
<published>2015-03-09T09:12:22Z</published>
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<id>urn:sha1:9ca0d35f24b1b1e21c609a521933fd4d6598f9ff</id>
<content type='text'>
T2080 rev1.1 also needs erratum a007186.

Signed-off-by: Shengzhou Liu &lt;Shengzhou.Liu@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
<entry>
<title>powerpc/mpc85xx: modify erratum A007186</title>
<updated>2014-12-05T16:06:09Z</updated>
<author>
<name>Zhao Qiang</name>
<email>B45475@freescale.com</email>
</author>
<published>2014-10-30T06:07:39Z</published>
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<id>urn:sha1:e7f533cd5972d762e0544a38c74fce495a9d9d2f</id>
<content type='text'>
T2080 v1.0 has this errata while v1.1 has fixed
this errata by hardware, add a new function has_errata_a007186
to check the SVR_SOC_VER, SVR_MAJ and SVR_MIN first,
if the sil has errata a007186, then run the errata code,
if not, doesn't run the code.

Signed-off-by: Zhao Qiang &lt;B45475@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
<entry>
<title>drivers: usb: fsl: Move USB Errata checking code</title>
<updated>2014-11-21T17:28:28Z</updated>
<author>
<name>Nikhil Badola</name>
<email>nikhil.badola@freescale.com</email>
</author>
<published>2014-09-30T05:52:43Z</published>
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<id>urn:sha1:c26c80a1a4e2e2e7e4c9806e9123bf027c02f711</id>
<content type='text'>
Move USB Errata checking code from "arch/powerpc" to architecture independent
file "fsl_usb.h" so that errata(s) become independent of the architecture.
For each erratum checking function for PPC arch, define a nop function for
non PPC arch for successful compilation in either case

Signed-off-by: Nikhil Badola &lt;nikhil.badola@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
<entry>
<title>powerpc/85xx: add T4080 SoC support</title>
<updated>2014-05-13T15:26:54Z</updated>
<author>
<name>Shengzhou Liu</name>
<email>Shengzhou.Liu@freescale.com</email>
</author>
<published>2014-04-25T08:31:22Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=5122dfae5d3cd68e0b6e5e08597df91ba79770aa'/>
<id>urn:sha1:5122dfae5d3cd68e0b6e5e08597df91ba79770aa</id>
<content type='text'>
The T4080 SoC is a low-power version of the T4160.
T4080 combines 4 dual-threaded Power Architecture e6500
cores with single cluster and two memory complexes.

Signed-off-by: Shengzhou Liu &lt;Shengzhou.Liu@freescale.com&gt;
</content>
</entry>
<entry>
<title>powerpc/t208x: enable errata A006261, A006593, A006379</title>
<updated>2014-05-13T15:26:54Z</updated>
<author>
<name>Shengzhou Liu</name>
<email>Shengzhou.Liu@freescale.com</email>
</author>
<published>2014-04-24T03:10:09Z</published>
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<id>urn:sha1:c665c473b605349b1c58890493255dd70e0b60fe</id>
<content type='text'>
Enable errata A006261, A006593, A006379 for T208x.
Additionally enable CONFIG_CMD_ERRATA for T2080RDB.

Signed-off-by: Shengzhou Liu &lt;Shengzhou.Liu@freescale.com&gt;
</content>
</entry>
<entry>
<title>fsl/usb: Workaround for USB erratum-A007075</title>
<updated>2014-04-23T00:58:48Z</updated>
<author>
<name>Nikhil Badola</name>
<email>nikhil.badola@freescale.com</email>
</author>
<published>2014-02-26T12:13:15Z</published>
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<id>urn:sha1:11856919f267d00155f571c75dd68ba1bb98729b</id>
<content type='text'>
Put a delay of 5 millisecond after reset so that ULPI phy
gets enough time to come out of reset. Erratum A007075 applies
to following SOCs and their variants, if any
        P1010 rev 1.0
        B4860 rev 1.0, 2.0
        P4080 rev 2.0, 3.0

Signed-off-by: Nikhil Badola &lt;nikhil.badola@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
<entry>
<title>powerpc/usb: Workaround for erratum-A006261</title>
<updated>2014-03-07T22:52:16Z</updated>
<author>
<name>Suresh Gupta</name>
<email>suresh.gupta@freescale.com</email>
</author>
<published>2014-02-26T08:59:12Z</published>
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<id>urn:sha1:9c641a872aa54edc97d69281f705819e96a5c90e</id>
<content type='text'>
USB spec says that the minimum disconnect threshold should be
	over 525 mV. However, internal USB PHY threshold value is below
	this specified value. Due to this some devices disconnect at
	run-time. Hence, phy settings are tweaked to increased disconnect
	threshold to be above 525mV by using this workaround.

Signed-off-by: Suresh Gupta &lt;suresh.gupta@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
<entry>
<title>powerpc/85xx: update erratum a006379</title>
<updated>2014-01-21T21:39:19Z</updated>
<author>
<name>Shengzhou Liu</name>
<email>Shengzhou.Liu@freescale.com</email>
</author>
<published>2014-01-06T05:23:21Z</published>
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<id>urn:sha1:842eaa13610e2b05fe905a659a3c2afc4e7eabec</id>
<content type='text'>
Enable Erratum A006379 for T2080, T2081, T4160, B4420.

Signed-off-by: Shengzhou Liu &lt;Shengzhou.Liu@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
<entry>
<title>powerpc/mpc85xx: Add workaround for erratum A006379</title>
<updated>2013-10-16T23:15:17Z</updated>
<author>
<name>York Sun</name>
<email>yorksun@freescale.com</email>
</author>
<published>2013-09-16T19:49:31Z</published>
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<id>urn:sha1:133fbfa9e6a81a59ab2d6848f0b111ebb2567a8a</id>
<content type='text'>
Erratum A006379 says CPCHDBCR0 bit field [10:14] has incorrect default
value after POR. The workaround is to set this field before enabling
CPC to 0x1e.

Erratum A006379 applies to
	T4240 rev 1.0
	B4860 rev 1.0, 2.0

Signed-off-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
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