u-boot.git/arch/powerpc/include/asm/fsl_secure_boot.h, branch v2014.07

powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T2080RDB

2014-05-13T15:26:54Z

Secure Boot Target is added for T2080RDB Changes: For Secure boot, CPC is configured as SRAM and used as house keeping area which needs to be disabled. So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T2080RDB. Signed-off-by: Aneesh Bansal

powerpc/mpc85xx: SECURE BOOT- secure boot target for t1040rdb

2014-05-13T15:24:32Z

T1040RDB.h file is removed and a unified file T104xRDB.h is created. Hence macro CONFIG_T1040 is renamed to CONFIG_T104x. Signed-off-by: Gaurav Kumar Rana Signed-off-by: Aneesh Bansal

powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T1040QDS and T1040RDB

2014-04-23T00:58:47Z

Secure Boot Target is added for T1040QDS and T1040RDB Changes: For Secure boot, CPC is configured as SRAM and used as house keeping area which needs to be disabled. So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T1040QDS and CONFIG_T1040RDB Signed-off-by: Gaurav Rana Signed-off-by: Aneesh Bansal Reviewed-by: York Sun

powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T2080QDS

2014-04-23T00:58:46Z

Secure Boot Target is added for T2080QDS Changes: For Secure boot, CPC is configured as SRAM and used as house keeping area which needs to be disabled. So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T2080QDS. Signed-off-by: Aneesh Bansal Reviewed-by: York Sun

powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T4240QDS and T4160QDS

2014-04-23T00:58:46Z

Secure Boot Target is added for T4240QDS and T4160QDS Changes: For Secure boot, CPC is configured as SRAM and used as house keeping area which needs to be disabled. So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T4240QDS. Signed-off-by: Aneesh Bansal Reviewed-by: York Sun

powerpc/mpc85xx: SECURE BOOT- Add secure boot target for B4860QDS

2014-04-23T00:58:46Z

Changes: 1. L2 cache is being invalidated by Boot ROM code for e6500 core. So removing the invalidation from start.S 2. Clear the LAW and corresponding configuration for CPC. Boot ROM code uses it as hosekeeping area. 3. For Secure boot, CPC is configured as SRAM and used as house keeping area. This configuration is to be disabled once in uboot. Earlier this disabling of CPC as SRAM was happening in cpu_init_r. As a result cache invalidation function was getting skipped in case CPC is configured as SRAM.This was causing random crashes. Signed-off-by: Ruchika Gupta Signed-off-by: Aneesh Bansal Reviewed-by: York Sun

powerpc/mpc85xx: SECURE BOOT- Add secure boot target for BSC9132QDS

2014-04-23T00:58:46Z

Add NOR, SPI and SD secure boot targets for BSC9132QDS. Changes: - Debug TLB entry is not required for Secure Boot Target. Signed-off-by: Aneesh Bansal Reviewed-by: York Sun

powerpc: add CONFIG_SECURE_BOOT condition into fsl_secure_boot.h

2013-10-16T23:13:10Z

This patch is for board config file not to add CONFIG_SECURE_BOOT condition for include the asm/fsl_secure_boot.h. Signed-off-by: Po Liu

Add GPL-2.0+ SPDX-License-Identifier to source files

2013-07-24T13:44:38Z

Signed-off-by: Wolfgang Denk [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini

SECURE BOOT - Removed deletion of TLB entries code

2013-05-24T21:54:14Z

Boot ROM code creates TLB entries for 3.5G space before entering the u-boot. Earlier we were deleting these entries after early initialization of CPU. In recent past, code has been added to invalidate all these entries before relocation of u-boot code. So this code to delete TLB entries after CPU initialization is no longer required. Signed-off-by: Ruchika Gupta Acked-by: Matthew McClintock Signed-off-by: Andy Fleming