u-boot.git/arch/powerpc/include/asm/fsl_secure_boot.h, branch v2015.04

SECURE_BOOT : enable esbc_validate command for powerpc and arm platforms.

2015-03-05T20:04:59Z

esbc_validate command uses various IP Blocks: Security Monitor, CAAM block and SFP registers. Hence the respective CONFIG's are enabled. Apart from these CONFIG_SHA_PROG_HW_ACCEL and CONFIG_RSA are also enabled. Signed-off-by: Gaurav Rana Reviewed-by: York Sun

powerpc/mpc85xx: Define PBI Flash Base for C29XPCIE Secure Boot

2015-01-16T17:30:12Z

CONFIG_SYS_PBI_FLASH_BASE is defined for Secure Boot on C29X Signed-off-by: Aneesh Bansal Reviewed-by: York Sun

powerpc/mpc85xx: Add T1024/T1023 SoC support

2014-12-05T16:06:14Z

Add support for Freescale T1024/T1023 SoC. The T1024 SoC includes the following function and features: - Two 64-bit Power architecture e5500 cores, up to 1.4GHz - private 256KB L2 cache each core and shared 256KB CoreNet platform cache (CPC) - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support - Data Path Acceleration Architecture (DPAA) incorporating acceleration - Four MAC for 1G/2.5G/10G network interfaces (RGMII, SGMII, QSGMII, XFI) - High-speed peripheral interfaces - Three PCI Express 2.0 controllers - Additional peripheral interfaces - One SATA 2.0 controller - Two USB 2.0 controllers with integrated PHY - Enhanced secure digital host controller (SD/eSDHC/eMMC) - Enhanced serial peripheral interface (eSPI) - Four I2C controllers - Four 2-pin UARTs or two 4-pin UARTs - Integrated Flash Controller supporting NAND and NOR flash - Two 8-channel DMA engines - Multicore programmable interrupt controller (PIC) - LCD interface (DIU) with 12 bit dual data rate - QUICC Engine block supporting TDM, HDLC, and UART - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) - Support for hardware virtualization and partitioning enforcement - QorIQ Platform's Trust Architecture 2.0 Differences between T1024 and T1023: Feature T1024 T1023 QUICC Engine: yes no DIU: yes no Deep Sleep: yes no I2C controller: 4 3 DDR: 64-bit 32-bit IFC: 32-bit 28-bit Signed-off-by: Shengzhou Liu Reviewed-by: York Sun

powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T2080RDB

2014-05-13T15:26:54Z

Secure Boot Target is added for T2080RDB Changes: For Secure boot, CPC is configured as SRAM and used as house keeping area which needs to be disabled. So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T2080RDB. Signed-off-by: Aneesh Bansal

powerpc/mpc85xx: SECURE BOOT- secure boot target for t1040rdb

2014-05-13T15:24:32Z

T1040RDB.h file is removed and a unified file T104xRDB.h is created. Hence macro CONFIG_T1040 is renamed to CONFIG_T104x. Signed-off-by: Gaurav Kumar Rana Signed-off-by: Aneesh Bansal

powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T1040QDS and T1040RDB

2014-04-23T00:58:47Z

Secure Boot Target is added for T1040QDS and T1040RDB Changes: For Secure boot, CPC is configured as SRAM and used as house keeping area which needs to be disabled. So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T1040QDS and CONFIG_T1040RDB Signed-off-by: Gaurav Rana Signed-off-by: Aneesh Bansal Reviewed-by: York Sun

powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T2080QDS

2014-04-23T00:58:46Z

Secure Boot Target is added for T2080QDS Changes: For Secure boot, CPC is configured as SRAM and used as house keeping area which needs to be disabled. So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T2080QDS. Signed-off-by: Aneesh Bansal Reviewed-by: York Sun

powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T4240QDS and T4160QDS

2014-04-23T00:58:46Z

Secure Boot Target is added for T4240QDS and T4160QDS Changes: For Secure boot, CPC is configured as SRAM and used as house keeping area which needs to be disabled. So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T4240QDS. Signed-off-by: Aneesh Bansal Reviewed-by: York Sun

powerpc/mpc85xx: SECURE BOOT- Add secure boot target for B4860QDS

2014-04-23T00:58:46Z

Changes: 1. L2 cache is being invalidated by Boot ROM code for e6500 core. So removing the invalidation from start.S 2. Clear the LAW and corresponding configuration for CPC. Boot ROM code uses it as hosekeeping area. 3. For Secure boot, CPC is configured as SRAM and used as house keeping area. This configuration is to be disabled once in uboot. Earlier this disabling of CPC as SRAM was happening in cpu_init_r. As a result cache invalidation function was getting skipped in case CPC is configured as SRAM.This was causing random crashes. Signed-off-by: Ruchika Gupta Signed-off-by: Aneesh Bansal Reviewed-by: York Sun

powerpc/mpc85xx: SECURE BOOT- Add secure boot target for BSC9132QDS

2014-04-23T00:58:46Z

Add NOR, SPI and SD secure boot targets for BSC9132QDS. Changes: - Debug TLB entry is not required for Secure Boot Target. Signed-off-by: Aneesh Bansal Reviewed-by: York Sun