u-boot.git/arch/powerpc/include/asm/processor.h, branch v2012.07

powerpc/mpc85xx: Ignore E bit for SVR_SOC_VER()

2012-07-06T22:30:33+00:00

We don't care E bit of SVR in most cases. Clear E bit for SVR_SOC_VER().
This will simplify the coding. Use IS_E_PROCESSOR() to identify SoC with
encryption. Remove all _E entries from SVR list and CPU list.

Signed-off-by: York Sun

powerpc/mpc85xx:Add BSC9131/BSC9130/BSC9231 Processor Support

2012-07-06T22:03:25+00:00

- BSC9131 is integrated device that targets Femto base station market.
   It combines Power Architecture e500v2 and DSP StarCore SC3850 core
   technologies with MAPLE-B2F baseband acceleration processing elements.
 - BSC9130 is exactly same as BSC9131 except that the max e500v2
   core and DSP core frequencies are 800M(these are 1G in case of 9131).
 - BSC9231 is similar to BSC9131 except no MAPLE

The BSC9131 SoC includes the following function and features:
    . Power Architecture subsystem including a e500 processor with 256-Kbyte shared
      L2 cache
    . StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache
    . The Multi Accelerator Platform Engine for Femto BaseStation Baseband
      Processing (MAPLE-B2F)
    . A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding,
     Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel processing,
     and CRC algorithms
    . Consists of accelerators for Convolution, Filtering, Turbo Encoding,
     Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix Inversion
     operations
    . DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with
     ECC, up to 400-MHz clock/800 MHz data rate
    . Dedicated security engine featuring trusted boot
    . DMA controller
    . OCNDMA with four bidirectional channels
    . Interfaces
    . Two triple-speed Gigabit Ethernet controllers featuring network acceleration
      including IEEE 1588. v2 hardware support and virtualization (eTSEC)
    . eTSEC 1 supports RGMII/RMII
    . eTSEC 2 supports RGMII
    . High-speed USB 2.0 host and device controller with ULPI interface
    . Enhanced secure digital (SD/MMC) host controller (eSDHC)
    . Antenna interface controller (AIC), supporting three industry standard
      JESD207/three custom ADI RF interfaces (two dual port and one single port)
      and three MAXIM's MaxPHY serial interfaces
    . ADI lanes support both full duplex FDD support and half duplex TDD support
    . Universal Subscriber Identity Module (USIM) interface that facilitates
      communication to SIM cards or Eurochip pre-paid phone cards
    . TDM with one TDM port
    . Two DUART, four eSPI, and two I2C controllers
    . Integrated Flash memory controller (IFC)
    . TDM with 256 channels
    . GPIO
    . Sixteen 32-bit timers

The DSP portion of the SoC consists of DSP core (SC3850) and various
accelerators pertaining to DSP operations.

This patch takes care of code pertaining to power side functionality only.

Signed-off-by: Ramneek Mehresh 
Signed-off-by: Priyanka Jain 
Signed-off-by: Akhil Goyal 
Signed-off-by: Poonam Aggrwal 
Signed-off-by: Rajan Srivastava 
Signed-off-by: Prabhakar Kushwaha

powerpc/85xx: Add support for Book-E MMU Arch v2.0

2011-11-08T14:36:51+00:00

A few of the config registers changed definition between MMU v1.0 and
MMUv2.0.  The new e6500 core from Freescale implements v2.0 of the
architecture.

Specifically, how we determine the size of TLB entries we support in the
variable size (or TLBCAM/TLB1) array is specified in a new register
(TLBnPS - TLB n Page size) instead of via TLBnCFG.

Signed-off-by: Kumar Gala

powerpc/p3060: Add SoC related support for P3060 platform

2011-10-03T14:36:28+00:00

Add P3060 SoC specific information:cores setup, LIODN setup, etc

The P3060 SoC combines six e500mc Power Architecture processor cores with
high-performance datapath acceleration architecture(DPAA), CoreNet fabric
infrastructure, as well as network and peripheral interfaces.

Signed-off-by: Shengzhou Liu 
Signed-off-by: Kumar Gala

powerpc/85xx: Cleanup how SVR_MAJ() is defined on MPC8536

2011-09-30T00:01:05+00:00

The MPC8536 seems to use only 3 bits for the major revision field in the
SVR rather than the 4 bits used by all other processors.  The most
significant bit is used as a mfg code on MPC8536.

Signed-off-by: Kumar Gala

powerpc/mp: add support for discontiguous cores

2011-09-30T00:01:05+00:00

Some SOCs have discontiguously-numbered cores, and so we can't determine the
valid core numbers via the FRR register any more.  We define
CPU_TYPE_ENTRY_MASK to specify a discontiguous core mask, and helper functions
to process the mask and enumerate over the set of valid cores.

Signed-off-by: Timur Tabi 
Signed-off-by: Kumar Gala

powerpc/85xx: Cleanup handling of PVR detection for e500/e500mc/e5500

2011-07-29T13:53:39+00:00

At some point we broke the detection of e500v1 class cores.  Fix that
and simply the code to just utilize PVR_VER() to have a single case
statement.

Signed-off-by: Kumar Gala

powerpc/85xx: Add P2041 processor support

2011-07-11T18:24:19+00:00

The P2041 is similar to P2040, however has a 10G port and backside L2

Signed-off-by: Kumar Gala

PPC405EX CHIP_21 erratum

2011-05-12T14:10:51+00:00

APM errata CHIP_21 for the 405EX/EXr (from the rev 1.09 document dated
4/27/11) states that rev D processors may wake up with the wrong feature
set.  This patch implements the APM-proposed workaround.

To enable this patch for your board, add the appropriate define for your
CPU to your board header file.  See kilauea.h for more information.  The
following variants are supported:

#define CONFIG_SYS_4xx_CHIP_21_405EX_NO_SECURITY
#define CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY
#define CONFIG_SYS_4xx_CHIP_21_405EXr_NO_SECURITY
#define CONFIG_SYS_4xx_CHIP_21_405EXr_SECURITY

Please note that if you select the wrong define, your board will not
boot, and JTAG will be required to recover.

Tested on custom boards using:

CONFIG_SYS_4xx_CHIP_21_405EX_NO_SECURITY  
CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY     

Signed-off-by: Steve Falco 
Acked-by: Dirk Eibach 
Signed-off-by: Stefan Roese

powerpc/85xx: Support for Freescale P1024/P1025 processor

2011-04-04T14:24:42+00:00

Add Support for Freescale P1024/P1025 (dual core) and
P1015/P1016 (single core) processors.

P1024 is a variant of P1020 processor with a core frequency from
400Mhz to 667Mhz and comes in a 561-pin wirebond power-BGA

P1025 is a variant of P1021 processor with a core frequency from
400Mhz to 667Mhz and comes in a 561-pin wirebond power-BGA

P1015 is a variant of P1024 processor with single core and P1016 is a
variant of P1025 processor with single core.

Added comments in config_mpc85xx.h to denote single core versions of
processors.

Signed-off-by: Jin Qing 
Signed-off-by: Li Yang 
Signed-off-by: Kumar Gala