u-boot.git/arch/powerpc/include/asm/processor.h, branch v2012.10

powerpc/85xx: clear out TLB on boot

2012-08-23T17:16:57+00:00

Instead of just shooting down the entry that covers CCSR, clear out
every TLB entry that isn't the one that we're executing out of.

Signed-off-by: Scott Wood 
Signed-off-by: Andy Fleming

Add e6500 processor detection

2012-08-23T17:16:54+00:00

Signed-off-by: York Sun 
Signed-off-by: Andy Fleming

powerpc/mpc8xxx: use topology registers to calculate number of cores

2012-08-23T17:16:54+00:00

We have actual topology infomation to find out exactly which core is present.
Calculate the number of cores if not specified.

Signed-off-by: Kumar Gala 
Signed-off-by: York Sun 
Signed-off-by: Andy Fleming

powerpc/fsl-corenet: work around erratum A004510

2012-08-23T17:16:54+00:00

Erratum A004510 says that under certain load conditions, modified
cache lines can be discarded, causing data corruption.

To work around this, several CCSR and DCSR register updates need to be
made in a careful manner, so that there is no other transaction in
corenet when the update is made.

The update is made from a locked cacheline, with a delay before to flush
any previous activity, and a delay after to flush the CCSR/DCSR update.
We can't use a readback because that would be another corenet
transaction, which is not allowed.

We lock the subsequent cacheline to prevent it from being fetched while
we're executing the previous cacheline.  It is filled with nops so that a
branch doesn't cause us to fetch another cacheline.

Ordinarily we are running in a cache-inhibited mapping at this point, so
we temporarily change that.  We make it guarded so that we should never
see a speculative load, and we never do an explicit load.  Thus, only the
I-cache should ever fill from this mapping, and we flush/unlock it
afterward.  Thus we should avoid problems from any potential cache
aliasing between inhibited and non-inhibited mappings.

NOTE that if PAMU is used with this patch, it will need to use a
dedicated LAW as described in the erratum.  This is the responsibility
of the OS that sets up PAMU.

Signed-off-by: Scott Wood 
Signed-off-by: Andy Fleming

powerpc/85xx: remove support for the Freescale P3060

2012-08-23T17:16:53+00:00

The P3060 was cancelled before it went into production, so there's no point
in supporting it.

Signed-off-by: Timur Tabi 
Signed-off-by: Andy Fleming

powerpc/mpc8xxx: Remove P1015 and P1016 from CPU list

2012-08-23T15:24:16+00:00

P1015 is the same as P1011 and P1016 is the same as P1012 from software
point of view. They have different packages but share SVRs.

Signed-off-by: York Sun 
Signed-off-by: Andy Fleming

powerpc/mpc85xx: Ignore E bit for BSC9130/1

2012-08-08T23:32:16+00:00

Commit 48f6a5c34 removed E bit. BSC9130/1 were left out due to patch apply
timing. Remove them now.

Signed-off-by: York Sun 
Signed-off-by: Andy Fleming

powerpc/mpc85xx: Ignore E bit for SVR_SOC_VER()

2012-07-06T22:30:33+00:00

We don't care E bit of SVR in most cases. Clear E bit for SVR_SOC_VER().
This will simplify the coding. Use IS_E_PROCESSOR() to identify SoC with
encryption. Remove all _E entries from SVR list and CPU list.

Signed-off-by: York Sun

powerpc/mpc85xx:Add BSC9131/BSC9130/BSC9231 Processor Support

2012-07-06T22:03:25+00:00

- BSC9131 is integrated device that targets Femto base station market.
   It combines Power Architecture e500v2 and DSP StarCore SC3850 core
   technologies with MAPLE-B2F baseband acceleration processing elements.
 - BSC9130 is exactly same as BSC9131 except that the max e500v2
   core and DSP core frequencies are 800M(these are 1G in case of 9131).
 - BSC9231 is similar to BSC9131 except no MAPLE

The BSC9131 SoC includes the following function and features:
    . Power Architecture subsystem including a e500 processor with 256-Kbyte shared
      L2 cache
    . StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache
    . The Multi Accelerator Platform Engine for Femto BaseStation Baseband
      Processing (MAPLE-B2F)
    . A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding,
     Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel processing,
     and CRC algorithms
    . Consists of accelerators for Convolution, Filtering, Turbo Encoding,
     Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix Inversion
     operations
    . DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with
     ECC, up to 400-MHz clock/800 MHz data rate
    . Dedicated security engine featuring trusted boot
    . DMA controller
    . OCNDMA with four bidirectional channels
    . Interfaces
    . Two triple-speed Gigabit Ethernet controllers featuring network acceleration
      including IEEE 1588. v2 hardware support and virtualization (eTSEC)
    . eTSEC 1 supports RGMII/RMII
    . eTSEC 2 supports RGMII
    . High-speed USB 2.0 host and device controller with ULPI interface
    . Enhanced secure digital (SD/MMC) host controller (eSDHC)
    . Antenna interface controller (AIC), supporting three industry standard
      JESD207/three custom ADI RF interfaces (two dual port and one single port)
      and three MAXIM's MaxPHY serial interfaces
    . ADI lanes support both full duplex FDD support and half duplex TDD support
    . Universal Subscriber Identity Module (USIM) interface that facilitates
      communication to SIM cards or Eurochip pre-paid phone cards
    . TDM with one TDM port
    . Two DUART, four eSPI, and two I2C controllers
    . Integrated Flash memory controller (IFC)
    . TDM with 256 channels
    . GPIO
    . Sixteen 32-bit timers

The DSP portion of the SoC consists of DSP core (SC3850) and various
accelerators pertaining to DSP operations.

This patch takes care of code pertaining to power side functionality only.

Signed-off-by: Ramneek Mehresh 
Signed-off-by: Priyanka Jain 
Signed-off-by: Akhil Goyal 
Signed-off-by: Poonam Aggrwal 
Signed-off-by: Rajan Srivastava 
Signed-off-by: Prabhakar Kushwaha

powerpc/85xx: Add support for Book-E MMU Arch v2.0

2011-11-08T14:36:51+00:00

A few of the config registers changed definition between MMU v1.0 and
MMUv2.0.  The new e6500 core from Freescale implements v2.0 of the
architecture.

Specifically, how we determine the size of TLB entries we support in the
variable size (or TLBCAM/TLB1) array is specified in a new register
(TLBnPS - TLB n Page size) instead of via TLBnCFG.

Signed-off-by: Kumar Gala