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<title>u-boot.git/arch/powerpc/include/asm/processor.h, branch v2014.10</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/powerpc/include/asm/processor.h?h=v2014.10</id>
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<updated>2014-08-01T21:18:07Z</updated>
<entry>
<title>powerpc: macros for e500mc timer regs added</title>
<updated>2014-08-01T21:18:07Z</updated>
<author>
<name>Boschung, Rainer</name>
<email>Rainer.Boschung@keymile.com</email>
</author>
<published>2014-06-03T07:05:13Z</published>
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<id>urn:sha1:60b295672d61fe79e6af3d9e4f3e8bd23bf3b4ad</id>
<content type='text'>
For e500mc cores the watchdog timer period has to be set by means of a
6bit value, that defines the bit of the timebase counter used to signal
a watchdog timer exception on its 0 to 1 transition.
The macro used to set the watchdog period TCR_WP, was redefined for e500mc
to support 6 WP setting.

The parameter (x) given to the macro specifies the prescaling factor of
the time base clock (fTB):

watchdog_period = 1/fTB * 2^x

Signed-off-by: Rainer Boschung &lt;rainer.boschung@keymile.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
<entry>
<title>powerpc/mpc85xx: Removed support for G4060</title>
<updated>2014-07-22T23:25:54Z</updated>
<author>
<name>Sandeep Singh</name>
<email>sandeep@freescale.com</email>
</author>
<published>2014-06-05T13:42:03Z</published>
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<id>urn:sha1:d43a386a91379816a6c26458daf3de92cc901b52</id>
<content type='text'>
G4060 has no PA cores, hence removing its support.

Signed-off-by: Sandeep Singh &lt;Sandeep@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
<entry>
<title>powerpc: hiddendragon: remove orphan board</title>
<updated>2014-05-30T18:03:24Z</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.m@jp.panasonic.com</email>
</author>
<published>2014-05-30T08:45:04Z</published>
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<id>urn:sha1:3fe1a8545b55d31a6db2d9e60d962c4f6e048913</id>
<content type='text'>
This board has been orphan for a while.
(Emails to its maintainer have been bouncing.)

Because MPC82xx family is old enough, nobody would pick up
the maintainership on it.

Signed-off-by: Masahiro Yamada &lt;yamada.m@jp.panasonic.com&gt;
Cc: Wolfgang Denx &lt;wd@denx.de&gt;
</content>
</entry>
<entry>
<title>powerpc/mpc85xx: Added B4460 support</title>
<updated>2014-05-16T21:24:26Z</updated>
<author>
<name>Shaveta Leekha</name>
<email>shaveta@freescale.com</email>
</author>
<published>2014-05-07T09:13:23Z</published>
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<id>urn:sha1:9c3fdd883a8c9aa32b52abf8ccc180bd4929826f</id>
<content type='text'>
B4460 differs from B4860 only in number of CPU cores,
hence used existing support for B4860.
B4460 has 2 PPC cores whereas B4860 has 4 PPC cores.

Signed-off-by: Shaveta Leekha &lt;shaveta@freescale.com&gt;
Signed-off-by: Sandeep Singh &lt;Sandeep@freescale.com&gt;
Signed-off-by: Poonam Aggrwal &lt;poonam.aggrwal@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
<entry>
<title>powerpc/85xx: add T4080 SoC support</title>
<updated>2014-05-13T15:26:54Z</updated>
<author>
<name>Shengzhou Liu</name>
<email>Shengzhou.Liu@freescale.com</email>
</author>
<published>2014-04-25T08:31:22Z</published>
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<id>urn:sha1:5122dfae5d3cd68e0b6e5e08597df91ba79770aa</id>
<content type='text'>
The T4080 SoC is a low-power version of the T4160.
T4080 combines 4 dual-threaded Power Architecture e6500
cores with single cluster and two memory complexes.

Signed-off-by: Shengzhou Liu &lt;Shengzhou.Liu@freescale.com&gt;
</content>
</entry>
<entry>
<title>powerpc: mpc8260: consolidate CONFIG_MPC8260 and CONFIG_8260</title>
<updated>2014-03-07T15:59:06Z</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.m@jp.panasonic.com</email>
</author>
<published>2014-03-05T08:40:10Z</published>
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<id>urn:sha1:58dac32764728f2f621377442d785936ec6925e8</id>
<content type='text'>
Before this commit, CONFIG_MPC8260 and CONFIG_8260
were used mixed-up.

All boards with mpc8260 cpu defined both of them:
  - CONFIG_MPC8260 was defined in board config headers
      and include/common.h
  - CONFIG_8260 was defined arch/powerpc/cpu/mpc8260/config.mk

We do not need to have both of them.
This commit keeps only CONFIG_MPC8260.

This commit does:
 - Delete CONFIG_8260 and CONFIG_MPC8260 definition
   in config headers and include/common.h
 - Rename CONFIG_8260 to CONFIG_MPC8260
    in arch/powerpc/cpu/mpc8260/config.mk.
 - Rename #ifdef CONFIG_8260 to #ifdef CONFIG_MPC8260

Signed-off-by: Masahiro Yamada &lt;yamada.m@jp.panasonic.com&gt;
Cc: Wolfgang Denk &lt;wd@denx.de&gt;
</content>
</entry>
<entry>
<title>powerpc/mpc85xx: Add T2080/T2081 SoC support</title>
<updated>2013-11-25T19:44:25Z</updated>
<author>
<name>Shengzhou Liu</name>
<email>Shengzhou.Liu@freescale.com</email>
</author>
<published>2013-11-22T09:39:10Z</published>
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<id>urn:sha1:629d6b32d6b9452b852fe79a195cca5b897fcad3</id>
<content type='text'>
Add support for Freescale T2080/T2081 SoC.

T2080 includes the following functions and features:
- Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
- 2MB L2 cache and 512KB CoreNet platform cache (CPC)
- Hierarchical interconnect fabric
- One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
- Data Path Acceleration Architecture (DPAA) incorporating acceleration
- 16 SerDes lanes up to 10.3125 GHz
- 8 mEMACs for network interfaces (four 1Gbps MACs and four 10Gbps/1Gbps MACs)
- High-speed peripheral interfaces
  - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
  - Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz
- Additional peripheral interfaces
  - Two serial ATA (SATA 2.0) controllers
  - Two high-speed USB 2.0 controllers with integrated PHY
  - Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC)
  - Enhanced serial peripheral interface (eSPI)
  - Four I2C controllers
  - Four 2-pin UARTs or two 4-pin UARTs
  - Integrated Flash Controller supporting NAND and NOR flash
- Three eight-channel DMA engines
- Support for hardware virtualization and partitioning enforcement
- QorIQ Platform's Trust Architecture 2.0

Differences between T2080 and T2081:
  Feature               T2080 T2081
  1G Ethernet numbers:  8     6
  10G Ethernet numbers: 4     2
  SerDes lanes:         16    8
  Serial RapidIO,RMan:  2     no
  SATA Controller:      2     no
  Aurora:               yes   no
  SoC Package:          896-pins 780-pins

Signed-off-by: Shengzhou Liu &lt;Shengzhou.Liu@freescale.com&gt;
Acked-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
<entry>
<title>include: delete include/linux/config.h</title>
<updated>2013-11-08T20:25:13Z</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.m@jp.panasonic.com</email>
</author>
<published>2013-10-07T07:04:18Z</published>
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<id>urn:sha1:643aae1406c93ddc64fcf8c136b47cdffd9c8ccd</id>
<content type='text'>
Linux Kernel abolished include/linux/config.h long time ago.
(around version v2.6.18..v2.6.19)

We don't need to provide Linux copatibility any more.

This commit deletes include/linux/config.h
and fixes source files not to include this.

Signed-off-by: Masahiro Yamada &lt;yamada.m@jp.panasonic.com&gt;
</content>
</entry>
<entry>
<title>ppc4xx: Remove support for PPC405CR CPUs</title>
<updated>2013-08-20T15:35:24Z</updated>
<author>
<name>Matthias Fuchs</name>
<email>matthias.fuchs@esd.eu</email>
</author>
<published>2013-08-07T10:10:38Z</published>
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<id>urn:sha1:3fb858891273945ce2238e6d4dac3363a1fb0853</id>
<content type='text'>
This patch removes support for the APM 405CR CPU.
This CPU is EOL and no board uses this chip.

Signed-off-by: Matthias Fuchs &lt;matthias.fuchs@esd.eu&gt;
</content>
</entry>
<entry>
<title>fsl_i2c: add workaround for the erratum I2C A004447</title>
<updated>2013-08-20T09:15:31Z</updated>
<author>
<name>Chunhe Lan</name>
<email>Chunhe.Lan@freescale.com</email>
</author>
<published>2013-08-16T07:10:37Z</published>
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<id>urn:sha1:9c3f77eb3bc0e1e24fc66bd41655fecddb6403ec</id>
<content type='text'>
This workaround is for the erratum I2C A004447. Device reference
manual provides a scheme that allows the I2C master controller
to generate nine SCL pulses, which enable an I2C slave device
that held SDA low to release SDA. However, due to this erratum,
this scheme no longer works. In addition, when I2C is used as
a source of the PBL, the state machine is not able to recover.

At the same time, delete the reduplicative definition of SVR_VER
and SVR_REV. The SVR_REV is the low 8 bits rather than the low 16
bits of svr. And we use the CONFIG_SYS_FSL_A004447_SVR_REV macro
instead of hard-code value 0x10, 0x11 and 0x20.

The CONFIG_SYS_FSL_A004447_SVR_REV = 0x00 represents that one
version of platform has this I2C errata. So enable this errata
by IS_SVR_REV(svr, maj, min) function.

Signed-off-by: Zhao Chenhui &lt;chenhui.zhao@freescale.com&gt;
Signed-off-by: Chunhe Lan &lt;Chunhe.Lan@freescale.com&gt;
Cc: Scott Wood &lt;scottwood@freescale.com&gt;
Cc: Heiko Schocher &lt;hs@denx.de&gt;
</content>
</entry>
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