u-boot.git/arch/powerpc/include/asm/processor.h, branch v2017.03

powerpc: mpc85xx: Implemente workaround for CPU erratum A-007907

2017-01-24T21:28:02Z

Core hang occurs when using L1 stashes. Workaround is to disable L1 stashes so software uses L2 cache for stashes instead. Reviewed-by: Chris Packham Signed-off-by: Darwin Dingel Cc: York Sun [York S: Move SYS_FSL_ERRATUM_A007907 to Kconfig] Reviewed-by: York Sun

powerpc: MPC8536: Move CONFIG_MPC8536 to Kconfig option

2016-11-24T07:42:04Z

Replace CONFIG_MPC8536 with ARCH_MPC8536 in Kconfig and clean up existing macros. Signed-off-by: York Sun

powerpc/mpc85xx: Add DSP side awareness for Freescale Heterogeneous SoCs

2015-03-04T18:15:29Z

The code provides framework for heterogeneous multicore chips based on StarCore and Power Architecture which are chasis-2 compliant, like B4860 and B4420 It will make u-boot recognize all non-ppc cores and peripherals like SC3900/DSP CPUs, MAPLE, CPRI and print their configuration in u-boot logs. Example boot logs of B4860QDS: U-Boot 2015.01-00232-geef6e36-dirty (Jan 19 2015 - 11:58:45) CPU0: B4860E, Version: 2.2, (0x86880022) Core: e6500, Version: 2.0, (0x80400120) Clock Configuration: CPU0:1600 MHz, CPU1:1600 MHz, CPU2:1600 MHz, CPU3:1600 MHz, DSP CPU0:1200 MHz, DSP CPU1:1200 MHz, DSP CPU2:1200 MHz, DSP CPU3:1200 MHz, DSP CPU4:1200 MHz, DSP CPU5:1200 MHz, CCB:666.667 MHz, DDR:933.333 MHz (1866.667 MT/s data rate) (Asynchronous), IFC:166.667 MHz CPRI:600 MHz MAPLE:600 MHz, MAPLE-ULB:800 MHz, MAPLE-eTVPE:1000 MHz FMAN1: 666.667 MHz QMAN: 333.333 MHz Top level changes include: (1) Top level CONFIG to identify HETEROGENUOUS clusters (2) CONFIGS for SC3900/DSP components (3) Global structures like "cpu_type" and "MPC85xx_SYS_INFO" updated for dsp cores and other components (3) APIs to get DSP num cores and their Mask like: cpu_dsp_mask, cpu_num_dspcores etc same as that of PowerPC (5) Code to fetch and print SC cores and other heterogenous device's frequencies (6) README added for the same Signed-off-by: Shaveta Leekha Reviewed-by: York Sun

powerpc: mpc824x: remove MPC824X cpu support

2015-01-05T17:08:55Z

All the MPC824X boards are still non-generic boards: A3000, CPC45, CU824, eXalion, MVBLUE, MUSENKI, Sandpoint824x, utx8245 Signed-off-by: Masahiro Yamada Cc: Wolfgang Denk Cc: Josef Wagner Cc: Torsten Demke Cc: Jim Thompson Cc: Greg Allen

powerpc/mpc85xx: Add T1024/T1023 SoC support

2014-12-05T16:06:14Z

Add support for Freescale T1024/T1023 SoC. The T1024 SoC includes the following function and features: - Two 64-bit Power architecture e5500 cores, up to 1.4GHz - private 256KB L2 cache each core and shared 256KB CoreNet platform cache (CPC) - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support - Data Path Acceleration Architecture (DPAA) incorporating acceleration - Four MAC for 1G/2.5G/10G network interfaces (RGMII, SGMII, QSGMII, XFI) - High-speed peripheral interfaces - Three PCI Express 2.0 controllers - Additional peripheral interfaces - One SATA 2.0 controller - Two USB 2.0 controllers with integrated PHY - Enhanced secure digital host controller (SD/eSDHC/eMMC) - Enhanced serial peripheral interface (eSPI) - Four I2C controllers - Four 2-pin UARTs or two 4-pin UARTs - Integrated Flash Controller supporting NAND and NOR flash - Two 8-channel DMA engines - Multicore programmable interrupt controller (PIC) - LCD interface (DIU) with 12 bit dual data rate - QUICC Engine block supporting TDM, HDLC, and UART - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) - Support for hardware virtualization and partitioning enforcement - QorIQ Platform's Trust Architecture 2.0 Differences between T1024 and T1023: Feature T1024 T1023 QUICC Engine: yes no DIU: yes no Deep Sleep: yes no I2C controller: 4 3 DDR: 64-bit 32-bit IFC: 32-bit 28-bit Signed-off-by: Shengzhou Liu Reviewed-by: York Sun

powerpc: macros for e500mc timer regs added

2014-08-01T21:18:07Z

For e500mc cores the watchdog timer period has to be set by means of a 6bit value, that defines the bit of the timebase counter used to signal a watchdog timer exception on its 0 to 1 transition. The macro used to set the watchdog period TCR_WP, was redefined for e500mc to support 6 WP setting. The parameter (x) given to the macro specifies the prescaling factor of the time base clock (fTB): watchdog_period = 1/fTB * 2^x Signed-off-by: Rainer Boschung Reviewed-by: York Sun

powerpc/mpc85xx: Removed support for G4060

2014-07-22T23:25:54Z

G4060 has no PA cores, hence removing its support. Signed-off-by: Sandeep Singh Reviewed-by: York Sun

powerpc: hiddendragon: remove orphan board

2014-05-30T18:03:24Z

This board has been orphan for a while. (Emails to its maintainer have been bouncing.) Because MPC82xx family is old enough, nobody would pick up the maintainership on it. Signed-off-by: Masahiro Yamada Cc: Wolfgang Denx

powerpc/mpc85xx: Added B4460 support

2014-05-16T21:24:26Z

B4460 differs from B4860 only in number of CPU cores, hence used existing support for B4860. B4460 has 2 PPC cores whereas B4860 has 4 PPC cores. Signed-off-by: Shaveta Leekha Signed-off-by: Sandeep Singh Signed-off-by: Poonam Aggrwal Reviewed-by: York Sun

powerpc/85xx: add T4080 SoC support

2014-05-13T15:26:54Z

The T4080 SoC is a low-power version of the T4160. T4080 combines 4 dual-threaded Power Architecture e6500 cores with single cluster and two memory complexes. Signed-off-by: Shengzhou Liu