<feed xmlns='http://www.w3.org/2005/Atom'>
<title>u-boot.git/arch/powerpc/include/asm, branch v2010.09</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/powerpc/include/asm?h=v2010.09</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/arch/powerpc/include/asm?h=v2010.09'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<updated>2010-08-19T07:06:13Z</updated>
<entry>
<title>powerpc/85xx: Rename Security Engine Job Queue to Job Ring to match docs</title>
<updated>2010-08-19T07:06:13Z</updated>
<author>
<name>Kumar Gala</name>
<email>galak@kernel.crashing.org</email>
</author>
<published>2010-08-18T04:12:37Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ed062e0f6c7ee8c56eb096fdd3e01712c53fc2e4'/>
<id>urn:sha1:ed062e0f6c7ee8c56eb096fdd3e01712c53fc2e4</id>
<content type='text'>
Official docs call it the Job Ring not Job Queue for the p4080 security
block.  Match the docs to reduce confusion.

Signed-off-by: Kim Phillips &lt;kim.phillips@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</content>
</entry>
<entry>
<title>powerpc/8xxx: share PIC defines among 85xx and 86xx</title>
<updated>2010-08-19T07:06:13Z</updated>
<author>
<name>Kim Phillips</name>
<email>kim.phillips@freescale.com</email>
</author>
<published>2010-08-09T23:39:57Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=680c613a5cc7be59a9123765c51287bc306df02f'/>
<id>urn:sha1:680c613a5cc7be59a9123765c51287bc306df02f</id>
<content type='text'>
fixes breakeage introduced by commit
a37c36f4e70bada297f281b0e542539ad43e50f6 "powerpc/8xxx: query
feature reporting register for num cores on unknown cpus"

Reported-by: Wolfgang Denk &lt;wd@denx.de&gt;
Signed-off-by: Kim Phillips &lt;kim.phillips@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</content>
</entry>
<entry>
<title>Merge branch 'master' of git://git.denx.de/u-boot-marvell</title>
<updated>2010-08-10T20:37:27Z</updated>
<author>
<name>Wolfgang Denk</name>
<email>wd@denx.de</email>
</author>
<published>2010-08-10T20:37:27Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=fe8d63c8c75acc87d398b2e181b9135d2ecfc05a'/>
<id>urn:sha1:fe8d63c8c75acc87d398b2e181b9135d2ecfc05a</id>
<content type='text'>
</content>
</entry>
<entry>
<title>ide: add configuration</title>
<updated>2010-08-07T23:47:05Z</updated>
<author>
<name>Albert Aribaud</name>
<email>[albert.aribaud@free.fr]</email>
</author>
<published>2010-08-07T23:47:05Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f2a37fcd9ba9d3d0aab5864141715596aff1de60'/>
<id>urn:sha1:f2a37fcd9ba9d3d0aab5864141715596aff1de60</id>
<content type='text'>
CONFIG_IDE_SWAP_IO

This configuration option replaces a complex conditional
in cmd_ide.c with an explicit define to be added to SoC or
board configs.

Signed-off-by: Albert Aribaud &lt;albert.aribaud@free.fr&gt;
</content>
</entry>
<entry>
<title>powerpc/8xxx: query feature reporting register for num cores on unknown cpus</title>
<updated>2010-08-01T16:18:45Z</updated>
<author>
<name>Kim Phillips</name>
<email>kim.phillips@freescale.com</email>
</author>
<published>2010-07-15T00:47:29Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=a37c36f4e70bada297f281b0e542539ad43e50f6'/>
<id>urn:sha1:a37c36f4e70bada297f281b0e542539ad43e50f6</id>
<content type='text'>
doing so helps avant garde users, such as those using simulators that
allow users to configure the number of cores, so as to not have to
manually adjust u-boot sources.  h/w should also be reliably setting
FRR NCPU in the future.

Signed-off-by: Kim Phillips &lt;kim.phillips@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</content>
</entry>
<entry>
<title>powerpc/8xxx: Enable DDR3 RDIMM support</title>
<updated>2010-07-26T18:16:10Z</updated>
<author>
<name>york</name>
<email>yorksun@freescale.com</email>
</author>
<published>2010-07-02T22:25:55Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=9490ff48648d969caeb70dbc6e506175f8699617'/>
<id>urn:sha1:9490ff48648d969caeb70dbc6e506175f8699617</id>
<content type='text'>
Enabled registered DIMMs using data from SPD. RDIMMs have registers
which need to be configured before using. The register configuration
words are stored in SPD byte 60~116 (JEDEC standard No.21-C). Software
should read those RCWs and put into DDR controller before initialization.

Signed-off-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
<entry>
<title>powerpc/8xxx: Enabled address hashing for 85xx</title>
<updated>2010-07-26T18:16:09Z</updated>
<author>
<name>york</name>
<email>yorksun@freescale.com</email>
</author>
<published>2010-07-02T22:25:54Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=7fd101c97b58dab7b0bd87f30c3dedb0db21d15f'/>
<id>urn:sha1:7fd101c97b58dab7b0bd87f30c3dedb0db21d15f</id>
<content type='text'>
For 85xx silicon which supports address hashing, it can be activated by
hwconfig.

Signed-off-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
<entry>
<title>powerpc/8xxx: Enable quad-rank DIMMs.</title>
<updated>2010-07-26T18:16:09Z</updated>
<author>
<name>york</name>
<email>yorksun@freescale.com</email>
</author>
<published>2010-07-02T22:25:53Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=5800e7ab32c200836e81ab2384817d93105561c5'/>
<id>urn:sha1:5800e7ab32c200836e81ab2384817d93105561c5</id>
<content type='text'>
Previous code presumes each DIMM has up to two rank (chip select). Newer
DDR controller supports up to four chip select on one DIMM.

Signed-off-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
<entry>
<title>powerpc/p4080: Add workaround for erratum CPU22</title>
<updated>2010-07-26T18:07:57Z</updated>
<author>
<name>Kumar Gala</name>
<email>galak@kernel.crashing.org</email>
</author>
<published>2010-05-06T03:35:27Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=fd3c9befa83eecf6e7c6ef03c501159fbf754143'/>
<id>urn:sha1:fd3c9befa83eecf6e7c6ef03c501159fbf754143</id>
<content type='text'>
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</content>
</entry>
<entry>
<title>powerpc/p4080: Add support for initializing SERDES</title>
<updated>2010-07-26T18:07:57Z</updated>
<author>
<name>Kumar Gala</name>
<email>galak@kernel.crashing.org</email>
</author>
<published>2010-07-13T03:51:29Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=34a8258fea40283426cf47c47008f9e6d2286080'/>
<id>urn:sha1:34a8258fea40283426cf47c47008f9e6d2286080</id>
<content type='text'>
Add support for initializing the SERDES blocks on CoreNet style QoriQ
devices and the p4080 specific SERDES tables to know which actual
componetns are enabled.

Additionally, split out the Frame Manger (FMAN) into its specific ethernet
ports instead of gross level of the full FMAN.

Signed-off-by: Li Yang &lt;leoli@freescale.com&gt;
Signed-off-by: Roy Zang &lt;tie-fei.zang@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</content>
</entry>
</feed>
