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<title>u-boot.git/arch/powerpc/include/asm, branch v2011.09</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
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<entry>
<title>Fix incorrect array size of phy settings for 405EX</title>
<updated>2011-09-19T09:51:21+00:00</updated>
<author>
<name>Weirich, Bernhard</name>
<email>Bernhard.Weirich@riedel.net</email>
</author>
<published>2011-09-08T16:27:38+00:00</published>
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<content type='text'>
Change bd_t-&gt;bi_phy* arrays from 1 to 2 for PPC405EX since
405EX has 2 ethernet interfaces.

Signed-off-by: Bernhard Weirich &lt;bernhard.weirich@riedel.net&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
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<pre>
Change bd_t-&gt;bi_phy* arrays from 1 to 2 for PPC405EX since
405EX has 2 ethernet interfaces.

Signed-off-by: Bernhard Weirich &lt;bernhard.weirich@riedel.net&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</pre>
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</content>
</entry>
<entry>
<title>powerpc/85xx: Cleanup handling of PVR detection for e500/e500mc/e5500</title>
<updated>2011-07-29T13:53:39+00:00</updated>
<author>
<name>Kumar Gala</name>
<email>galak@kernel.crashing.org</email>
</author>
<published>2011-07-25T14:28:39+00:00</published>
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<content type='text'>
At some point we broke the detection of e500v1 class cores.  Fix that
and simply the code to just utilize PVR_VER() to have a single case
statement.

Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
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<pre>
At some point we broke the detection of e500v1 class cores.  Fix that
and simply the code to just utilize PVR_VER() to have a single case
statement.

Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</pre>
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</content>
</entry>
<entry>
<title>powerpc/85xx: Adding configuration for DCSRCR to enable 32M access</title>
<updated>2011-07-29T13:53:37+00:00</updated>
<author>
<name>Stephen George</name>
<email>stephen.george@freescale.com</email>
</author>
<published>2011-07-20T14:47:26+00:00</published>
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<id>f110fe940c7bca04cf0104952555fd931b075fac</id>
<content type='text'>
Configuring DCSRCR to define the DCSR space to be 1G instead
of the default 4M. DCSRCR only allows selection of either 4M
or 1G.
Most DCSR registers are within 4M but the Nexus trace buffer
is located at offset 16M within the DCSR.

Configuring the LAW to be 32M to allow access to the Nexus
trace buffer. No TLB modification is required since accessing
the Nexus trace buffer from within u-boot is not required.

Signed-off-by: Stephen George &lt;stephen.george@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
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<pre>
Configuring DCSRCR to define the DCSR space to be 1G instead
of the default 4M. DCSRCR only allows selection of either 4M
or 1G.
Most DCSR registers are within 4M but the Nexus trace buffer
is located at offset 16M within the DCSR.

Configuring the LAW to be 32M to allow access to the Nexus
trace buffer. No TLB modification is required since accessing
the Nexus trace buffer from within u-boot is not required.

Signed-off-by: Stephen George &lt;stephen.george@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</pre>
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</content>
</entry>
<entry>
<title>cleanup: Fix typos and misspellings in various files.</title>
<updated>2011-07-28T19:27:36+00:00</updated>
<author>
<name>Mike Williams</name>
<email>mike@mikebwilliams.com</email>
</author>
<published>2011-07-22T04:01:30+00:00</published>
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<id>1626308797ac4184e73e56d275a1b8da11a62d5b</id>
<content type='text'>
Recieve/Receive
recieve/receive
Interupt/Interrupt
interupt/interrupt
Addres/Address
addres/address

Signed-off-by: Mike Williams &lt;mike@mikebwilliams.com&gt;
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<pre>
Recieve/Receive
recieve/receive
Interupt/Interrupt
interupt/interrupt
Addres/Address
addres/address

Signed-off-by: Mike Williams &lt;mike@mikebwilliams.com&gt;
</pre>
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</content>
</entry>
<entry>
<title>powerpc/mpc85xx: Add clear_ddr_tlbs function</title>
<updated>2011-07-22T08:07:47+00:00</updated>
<author>
<name>Becky Bruce</name>
<email>beckyb@kernel.crashing.org</email>
</author>
<published>2011-07-18T23:49:15+00:00</published>
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<content type='text'>
This is useful when we just want to wipe out the TLBs.  There's currently
a function that resets the ddr tlbs to a different value; it is changed to
utilize this function.  The new function can be used in conjunction with
setup_ddr_tlbs() for a board to temporarily map/unmap the DDR address
range as needed.

Signed-off-by: Becky Bruce &lt;beckyb@kernel.crashing.org&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
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<pre>
This is useful when we just want to wipe out the TLBs.  There's currently
a function that resets the ddr tlbs to a different value; it is changed to
utilize this function.  The new function can be used in conjunction with
setup_ddr_tlbs() for a board to temporarily map/unmap the DDR address
range as needed.

Signed-off-by: Becky Bruce &lt;beckyb@kernel.crashing.org&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</pre>
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</content>
</entry>
<entry>
<title>powerpc/mpc8xxx: Allow override DDR read-to-write turnaround time</title>
<updated>2011-07-11T18:24:20+00:00</updated>
<author>
<name>York Sun</name>
<email>yorksun@freescale.com</email>
</author>
<published>2011-05-27T05:44:28+00:00</published>
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<id>23f9670f1aee936ca468d2d0ddb0f025defde626</id>
<content type='text'>
Add this option to allow boards to override the default read-to-write
turnaround time for better performance.

Signed-off-by: York Sun &lt;yorksun@freescale.com&gt;
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<pre>
Add this option to allow boards to override the default read-to-write
turnaround time for better performance.

Signed-off-by: York Sun &lt;yorksun@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc/85xx: Fix pin muxing for second USB controller</title>
<updated>2011-07-11T18:24:20+00:00</updated>
<author>
<name>Felix Radensky</name>
<email>felix@embedded-sol.com</email>
</author>
<published>2011-06-27T06:39:29+00:00</published>
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<id>aeb6716a12c68644d6dc1e798b724086c3cfcd24</id>
<content type='text'>
On P1022/P1013 second USB controller is muxed with second
Ethernet controller. The current code to enable second USB
fails to properly clear pinmux bits used by ethernet. As a
result, Linux freezes when this controller is used. This
patch fixes the problem.

Signed-off-by: Felix Radensky &lt;felix@embedded-sol.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</content>
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<pre>
On P1022/P1013 second USB controller is muxed with second
Ethernet controller. The current code to enable second USB
fails to properly clear pinmux bits used by ethernet. As a
result, Linux freezes when this controller is used. This
patch fixes the problem.

Signed-off-by: Felix Radensky &lt;felix@embedded-sol.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc/mpc8xxx: Add 16-bit support for DDR3</title>
<updated>2011-07-11T18:24:20+00:00</updated>
<author>
<name>York Sun</name>
<email>yorksun@freescale.com</email>
</author>
<published>2011-05-26T23:25:51+00:00</published>
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<id>51d498f17517c541e262ad14b043095dea6d0fe7</id>
<content type='text'>
Add support for 16-bit DDR bus. Also deal with system using 64- and 32-bit
DDR devices.

Signed-off-by: York Sun &lt;yorksun@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
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<pre>
Add support for 16-bit DDR bus. Also deal with system using 64- and 32-bit
DDR devices.

Signed-off-by: York Sun &lt;yorksun@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc/85xx: Add P2041 processor support</title>
<updated>2011-07-11T18:24:19+00:00</updated>
<author>
<name>Kumar Gala</name>
<email>galak@kernel.crashing.org</email>
</author>
<published>2011-05-13T06:16:07+00:00</published>
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<content type='text'>
The P2041 is similar to P2040, however has a 10G port and backside L2

Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
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<pre>
The P2041 is similar to P2040, however has a 10G port and backside L2

Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</pre>
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</content>
</entry>
<entry>
<title>powerpc/fsl_pci: Fix device tree fixups for newer platforms</title>
<updated>2011-05-20T05:48:41+00:00</updated>
<author>
<name>Kumar Gala</name>
<email>galak@kernel.crashing.org</email>
</author>
<published>2011-05-20T05:39:21+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=8f29084a4f020ddc2d15a0f374f08f80aa8b39a0'/>
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<content type='text'>
We assumed that only a small set of compatiable strings would be needed
to find the PCIe device tree nodes to be fixed up.  However on newer
platforms the simple rules no longer work.  We need to allow specifying
the PCIe compatiable string for each individual SoC.

We introduce CONFIG_SYS_FSL_PCIE_COMPAT for this purpose and set it if
the default isn't sufficient.

Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
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<pre>
We assumed that only a small set of compatiable strings would be needed
to find the PCIe device tree nodes to be fixed up.  However on newer
platforms the simple rules no longer work.  We need to allow specifying
the PCIe compatiable string for each individual SoC.

We introduce CONFIG_SYS_FSL_PCIE_COMPAT for this purpose and set it if
the default isn't sufficient.

Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</pre>
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