u-boot.git/arch/powerpc/include/asm, branch v2014.04

mmc:eSDHC: Workaround for data timeout issue on Txxx SoC

2014-04-02T10:25:01Z

1. The Data timeout counter value in eSDHC_SYSCTL register is not working as it should be, so add quirks to enable this workaround to fix it to the max value 0xE. 2. Add CONFIG_SYS_FSL_ERRATUM_ESDHC111 to enable its workaround. * Update of patch for change mmc interface by Pantelis Antoniou Signed-off-by: Haijun Zhang Acked-by: Pantelis Antoniou

Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

2014-03-08T01:54:22Z

powerpc/mpc85xx: Add SCFG_PIXCLKCR register support for T1040

2014-03-07T22:53:29Z

T1040 SoC has SCFG (Supplement Configuration) Block which provides chip specific configuration and status support. The base address of SCFG block in T1040 is 0xfc000. SCFG contains SCFG_PIXCLKCR (DIU pixel clock control register) at offset 0x28. Add definition of -SCFG block -SCFG_PIXCLKCR register -Bits definition of SCFG_PIXCLK register Signed-off-by: Priyanka Jain Reviewed-by: York Sun

powerpc/usb: Workaround for erratum-A006261

2014-03-07T22:52:16Z

USB spec says that the minimum disconnect threshold should be over 525 mV. However, internal USB PHY threshold value is below this specified value. Due to this some devices disconnect at run-time. Hence, phy settings are tweaked to increased disconnect threshold to be above 525mV by using this workaround. Signed-off-by: Suresh Gupta Reviewed-by: York Sun

powerpc/b4860: Add workaround for errata A006384 and A006475

2014-03-07T22:52:01Z

SerDes PLLs may not lock reliably at 5 G VCO configuration(A006384) and at cold temperatures(A006475), workaround recalibrate the PLLs with some SerDes configuration Both these errata are only applicable for b4 rev1. So, make workaround for these errata conditional, depending upon soc version. Signed-off-by: Shaveta Leekha Reviewed-by: York Sun

B4860/B4420: Add PLL_NUM define for B4420/B4860 to use SerDes2 Refclks re-configuration

2014-03-07T22:50:10Z

B4860 has two PLL per SerDes whereas B4420 has one PLL per SerDes, add their defines in arch/powerpc/include/asm/config_mpc85xx.h Signed-off-by: Shaveta Leekha Reviewed-by: York Sun

board/b4860qds: Add support to make PCIe SATA work on B4860QDS

2014-03-07T22:49:45Z

1) SerDes2 Refclks have been set properly to make PCIe SATA to work as it work on SerDes refclk of 100MHz 2) Mask the SerDes's device reset request before changing the Refclks for SerDes1 and SerDes2 for PLL locks to happen properly, device reset request bit unmasked after SerDes refclks configuration Signed-off-by: Shaveta Leekha Reviewed-by: York Sun

powerpc: mpc8260: consolidate CONFIG_MPC8260 and CONFIG_8260

2014-03-07T15:59:06Z

Before this commit, CONFIG_MPC8260 and CONFIG_8260 were used mixed-up. All boards with mpc8260 cpu defined both of them: - CONFIG_MPC8260 was defined in board config headers and include/common.h - CONFIG_8260 was defined arch/powerpc/cpu/mpc8260/config.mk We do not need to have both of them. This commit keeps only CONFIG_MPC8260. This commit does: - Delete CONFIG_8260 and CONFIG_MPC8260 definition in config headers and include/common.h - Rename CONFIG_8260 to CONFIG_MPC8260 in arch/powerpc/cpu/mpc8260/config.mk. - Rename #ifdef CONFIG_8260 to #ifdef CONFIG_MPC8260 Signed-off-by: Masahiro Yamada Cc: Wolfgang Denk

driver/ifc:Change accessor function to take care of endianness

2014-02-03T16:38:51Z

IFC registers can be of type Little Endian or big Endian depending upon Freescale SoC. Here SoC defines the register type of IFC IP. So update acessor functions with common IFC acessor functions to take care both type of endianness. Signed-off-by: Prabhakar Kushwaha Acked-by: York Sun

powerpc/usb: Enable dual phy for T1040

2014-02-03T16:38:49Z

Define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE macro for enabling dual phy in t1040 Signed-off-by: Nikhil Badola Reviewed-by: York Sun