u-boot.git/arch/powerpc/include/asm, branch v2014.10

powerpc: ppc4xx: remove board support for bluestone

2014-10-10T13:44:43Z

This board has been orphaned for more than 6 months. It is the last board defining CONFIG_APM821XX. The code inside #ifdef CONFIG_APM821XX should be removed too. Signed-off-by: Masahiro Yamada

net: Merge asm/fsl_enet.h into fsl_mdio.h

2014-09-08T17:30:33Z

fsl_enet.h defines the mapping of the usual MII management registers, which are included in the MDIO register block common to Freescale ethernet controllers. So it shouldn't depend on the CPU architecture but it should be actually part of the arch independent fsl_mdio.h. To remove the arch dependency, merge the content of asm/fsl_enet.h into fsl_mdio.h. Some files (like fm_eth.h) were simply including fsl_enet.h only for phy.h. These were updated to include phy.h instead. Signed-off-by: Claudiu Manoil

powerpc: macros for e500mc timer regs added

2014-08-01T21:18:07Z

For e500mc cores the watchdog timer period has to be set by means of a 6bit value, that defines the bit of the timebase counter used to signal a watchdog timer exception on its 0 to 1 transition. The macro used to set the watchdog period TCR_WP, was redefined for e500mc to support 6 WP setting. The parameter (x) given to the macro specifies the prescaling factor of the time base clock (fTB): watchdog_period = 1/fTB * 2^x Signed-off-by: Rainer Boschung Reviewed-by: York Sun

mpc85xx/t104x: Enable L2 and CPC cache when resume

2014-07-22T23:25:55Z

When resume from deep sleep, uboot needs to enable L2 and CPC cache, or they would be keeping unusable in kernel because kernel didn't enble or initialized them. This patch didn't change the existing L2 cache enabling code, just put them in a function. Signed-off-by: Tang Yuantian Reviewed-by: York Sun

powerpc/t4240qds: fix offset of serdes when checking reference clock

2014-07-22T23:25:55Z

T4240 has 4 serdes, each serdes has 4k memory space, two PLLs. We use PLL1CR0 to check the serdes reference clock. Signed-off-by: Shaohui Xie Reviewed-by: York Sun

driver/ddr: Fix DDR4 driver for ARM

2014-07-22T23:25:54Z

Previously the driver was only tested on Power SoCs. Different barrier instructions are needed for ARM SoCs. Signed-off-by: York Sun

powerpc/mpc85xx: Removed support for G4060

2014-07-22T23:25:54Z

G4060 has no PA cores, hence removing its support. Signed-off-by: Sandeep Singh Reviewed-by: York Sun

qe: move immap_qe.h from arch directory into common directory

2014-07-22T23:25:54Z

ls1021 is arm-core and supports qe too. Move immap_qe.h into common directory for both arm and powerpc. Signed-off-by: Zhao Qiang Reviewed-by: York Sun

powerpc/mpc85xx: Add workaround to enable TDM on T1040

2014-06-05T20:45:07Z

This is a workaround for 32 bit hardware limitation of TDM. T1040 has 36 bit physical addressing, TDM DMAC register are 32 bit wide but need to store address of CCSR space which lies beyond 32 bit address range. This workaround creats a LAW to enable access of TDM DMA to CCSR by mapping CCSR to overlap with DDR. A hole of 16M is created in memory using device tree. This workaround law is set only if "tdm" is defined in hwconfig. Also disable POST tests and add LIODN for TDM Signed-off-by: Sandeep Singh Reviewed-by: York Sun

powerpc/serdes: Add the workaround for erratum A-007186

2014-06-05T20:45:07Z

SerDes PLL is calibrated at reset. When the junction temperature delta from the time the PLL is calibrated exceeds +56C/-66C, jitter may increase and can cause PLL to unlock. This workaround overwrite the SerDes registers with new values, to calibrate SerDes registers. These values are known to work fine for all temperature ranges. This workaround is valid for B4, T4 and T2 platforms, so added in their config. Signed-off-by: Shaveta Leekha Signed-off-by: Poonam Aggrwal [York Sun: replaced typedef ccsr_sfp_regs_t with struct ccsr_sfp_regs] Reviewed-by: York Sun