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<title>u-boot.git/arch/powerpc/include/asm, branch v2015.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/powerpc/include/asm?h=v2015.01</id>
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<updated>2015-01-05T17:08:55Z</updated>
<entry>
<title>powerpc: mpc824x: remove MPC824X cpu support</title>
<updated>2015-01-05T17:08:55Z</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.m@jp.panasonic.com</email>
</author>
<published>2014-12-15T14:26:31Z</published>
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<id>urn:sha1:d622ac39274a949b6445f1bfd92dc1644014388b</id>
<content type='text'>
All the MPC824X boards are still non-generic boards:
A3000, CPC45, CU824, eXalion, MVBLUE, MUSENKI, Sandpoint824x, utx8245

Signed-off-by: Masahiro Yamada &lt;yamada.m@jp.panasonic.com&gt;
Cc: Wolfgang Denk &lt;wd@denx.de&gt;
Cc: Josef Wagner &lt;Wagner@Microsys.de&gt;
Cc: Torsten Demke &lt;torsten.demke@fci.com&gt;
Cc: Jim Thompson &lt;jim@musenki.com&gt;
Cc: Greg Allen &lt;gallen@arlut.utexas.edu&gt;
</content>
</entry>
<entry>
<title>mpc8xx: remove lwmon board support</title>
<updated>2015-01-05T17:08:52Z</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.m@jp.panasonic.com</email>
</author>
<published>2014-12-15T14:26:14Z</published>
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<id>urn:sha1:acc2372db020b9415142e93a1c30f57c1d3aa5c2</id>
<content type='text'>
This board is still a non-generic board.

Signed-off-by: Masahiro Yamada &lt;yamada.m@jp.panasonic.com&gt;
Cc: Wolfgang Denk &lt;wd@denx.de&gt;
</content>
</entry>
<entry>
<title>powerpc/mpc85xx: use correct dma compatible for several SoCs</title>
<updated>2014-12-05T16:06:16Z</updated>
<author>
<name>Tudor Laurentiu</name>
<email>b10716@freescale.com</email>
</author>
<published>2014-11-20T10:09:31Z</published>
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<id>urn:sha1:8d3eaa970968d744771948a7188b07cb7ea4ea8a</id>
<content type='text'>
Newer qoriq socs have an updated dma ip block with a
different compatible. Let's make sure we use the proper
string so that the dmas get their liodn.
In order to have the means to specify the compatible
string, the liodn setting macros were updated to receive
a new parameter for it.
The following SoCs were changed to use the new compatible:
 T1023/4, T1040, T2080/1, T4240, B4860.

Signed-off-by: Laurentiu Tudor &lt;Laurentiu.Tudor@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
<entry>
<title>t1024qds: increase IO drive strength</title>
<updated>2014-12-05T16:06:16Z</updated>
<author>
<name>Shengzhou Liu</name>
<email>Shengzhou.Liu@freescale.com</email>
</author>
<published>2014-11-24T09:12:00Z</published>
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<id>urn:sha1:5818643bf4788062594cc0b1b188400f2d5fb211</id>
<content type='text'>
Increase IO drive strength to fix FCS error on RGMII ports
on T1024QDS.

Signed-off-by: Shengzhou Liu &lt;Shengzhou.Liu@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
<entry>
<title>net/fman: update 10GEC to fit new SoC</title>
<updated>2014-12-05T16:06:15Z</updated>
<author>
<name>Shengzhou Liu</name>
<email>Shengzhou.Liu@freescale.com</email>
</author>
<published>2014-11-24T09:11:57Z</published>
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<id>urn:sha1:cc19c25e2752bb8b446463eb627e258e659d73d9</id>
<content type='text'>
fm_standard_init() initializes each 10G port by FM_TGEC_INFO_INITIALIZER.
but it needs different implementation of FM_TGEC_INFO_INITIALIZER on different SoCs.
on SoCs earlier(e.g. T4240, T2080), the notation between 10GEC and MAC as below:
	10GEC1-&gt;MAC9, 10GEC2-&gt;MAC10, 10GEC3-&gt;MAC1, 10GEC4-&gt;MAC2
on SoCs later(e.g. T1024, etc), the notation between 10GEC and MAC as below:
	10GEC1-&gt;MAC1, 10GEC2-&gt;MAC2

so we introduce CONFIG_FSL_FM_10GEC_REGULAR_NOTATION to fit the new SoCs on
which 10GEC enumeration is consistent with MAC enumeration.

Signed-off-by: Shengzhou Liu &lt;Shengzhou.Liu@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
<entry>
<title>powerpc/mpc85xx: Add T1024/T1023 SoC support</title>
<updated>2014-12-05T16:06:14Z</updated>
<author>
<name>Shengzhou Liu</name>
<email>Shengzhou.Liu@freescale.com</email>
</author>
<published>2014-11-24T09:11:54Z</published>
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<id>urn:sha1:f605079041079cb4e84693110e26086f8d1a8bcd</id>
<content type='text'>
Add support for Freescale T1024/T1023 SoC.

The T1024 SoC includes the following function and features:
- Two 64-bit Power architecture e5500 cores, up to 1.4GHz
- private 256KB L2 cache each core and shared 256KB CoreNet platform cache (CPC)
- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support
- Data Path Acceleration Architecture (DPAA) incorporating acceleration
- Four MAC for 1G/2.5G/10G network interfaces (RGMII, SGMII, QSGMII, XFI)
- High-speed peripheral interfaces
  - Three PCI Express 2.0 controllers
- Additional peripheral interfaces
  - One SATA 2.0 controller
  - Two USB 2.0 controllers with integrated PHY
  - Enhanced secure digital host controller (SD/eSDHC/eMMC)
  - Enhanced serial peripheral interface (eSPI)
  - Four I2C controllers
  - Four 2-pin UARTs or two 4-pin UARTs
  - Integrated Flash Controller supporting NAND and NOR flash
- Two 8-channel DMA engines
- Multicore programmable interrupt controller (PIC)
- LCD interface (DIU) with 12 bit dual data rate
- QUICC Engine block supporting TDM, HDLC, and UART
- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
- Support for hardware virtualization and partitioning enforcement
- QorIQ Platform's Trust Architecture 2.0

Differences between T1024 and T1023:
  Feature         T1024  T1023
  QUICC Engine:   yes    no
  DIU:            yes    no
  Deep Sleep:     yes    no
  I2C controller: 4      3
  DDR:            64-bit 32-bit
  IFC:            32-bit 28-bit

Signed-off-by: Shengzhou Liu &lt;Shengzhou.Liu@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
<entry>
<title>powerpc/mpc85xx: modify erratum A007186</title>
<updated>2014-12-05T16:06:09Z</updated>
<author>
<name>Zhao Qiang</name>
<email>B45475@freescale.com</email>
</author>
<published>2014-10-30T06:07:39Z</published>
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<id>urn:sha1:e7f533cd5972d762e0544a38c74fce495a9d9d2f</id>
<content type='text'>
T2080 v1.0 has this errata while v1.1 has fixed
this errata by hardware, add a new function has_errata_a007186
to check the SVR_SOC_VER, SVR_MAJ and SVR_MIN first,
if the sil has errata a007186, then run the errata code,
if not, doesn't run the code.

Signed-off-by: Zhao Qiang &lt;B45475@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
<entry>
<title>powerpc/mpc85xx:Put errata number for T104x NAND boot issue</title>
<updated>2014-12-05T16:06:08Z</updated>
<author>
<name>Prabhakar Kushwaha</name>
<email>prabhakar@freescale.com</email>
</author>
<published>2014-10-29T17:03:09Z</published>
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<id>urn:sha1:9f074e67f5a2131336ff1838f2a82e0c2e15d33c</id>
<content type='text'>
When device is configured to load RCW from NAND flash IFC_A[16:31] are driven
low after RCW loading. Hence Devices connected on IFC_CS[1:7] and using
IFC_A[16:31] lines are not accessible.

Workaround is already in-place.
Put the errata number to adhere errata handling framework.

Signed-off-by: Prabhakar Kushwaha &lt;prabhakar@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
<entry>
<title>Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq</title>
<updated>2014-11-26T16:23:26Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@ti.com</email>
</author>
<published>2014-11-25T21:51:47Z</published>
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<id>urn:sha1:85bafb6da4dddfffa78479aa49a72ae48578a4ce</id>
<content type='text'>
</content>
</entry>
<entry>
<title>drivers : usb: fsl: Implement usb Erratum A007798 workaround</title>
<updated>2014-11-24T17:27:04Z</updated>
<author>
<name>Nikhil Badola</name>
<email>nikhil.badola@freescale.com</email>
</author>
<published>2014-10-17T03:42:07Z</published>
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<id>urn:sha1:f3dff695e155469c2c62edb7f3d571df8b3b20ad</id>
<content type='text'>
Set TXFIFOTHRESH to adjust ddr pipeline delay for successful large
usb writes

Signed-off-by: Nikhil Badola &lt;nikhil.badola@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
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