u-boot.git/arch/powerpc/include/asm, branch v2015.04

SECURE_BOOT : enable esbc_validate command for powerpc and arm platforms.

2015-03-05T20:04:59Z

esbc_validate command uses various IP Blocks: Security Monitor, CAAM block and SFP registers. Hence the respective CONFIG's are enabled. Apart from these CONFIG_SHA_PROG_HW_ACCEL and CONFIG_RSA are also enabled. Signed-off-by: Gaurav Rana Reviewed-by: York Sun

fsl_sfp : Move ccsr_sfp_regs definition to common include

2015-03-05T20:04:59Z

Freescale sfp has been used for mpc8xxx. It will be used for ARM-based SoC as well. This patch moves the CCSR defintion of sfp_regs to common include. This patch also defines ccsr_sfp_regs definition for newer versions of SFP. Signed-off-by: Ruchika Gupta Signed-off-by: Gaurav Rana Reviewed-by: York Sun

powerpc: 85xx: Modify CONFIG_USB_MAX_CONTROLLER_COUNT for P1022DS

2015-03-04T18:15:29Z

Modify CONFIG_USB_MAX_CONTROLLER_COUNT value to 1 on P1022DS. As ETSEC2 and USB2 are muxed; thus if ETSEC2 is enabled, the system bus hangs on USB2 if ETSEC2 is enabled but "usb start" command is issued. Hence making default controller count to 1 to avoid system hang. Signed-off-by: Nikhil Badola Reviewed-by: Yusong Sun

powerpc/mpc85xx: Add DSP side awareness for Freescale Heterogeneous SoCs

2015-03-04T18:15:29Z

The code provides framework for heterogeneous multicore chips based on StarCore and Power Architecture which are chasis-2 compliant, like B4860 and B4420 It will make u-boot recognize all non-ppc cores and peripherals like SC3900/DSP CPUs, MAPLE, CPRI and print their configuration in u-boot logs. Example boot logs of B4860QDS: U-Boot 2015.01-00232-geef6e36-dirty (Jan 19 2015 - 11:58:45) CPU0: B4860E, Version: 2.2, (0x86880022) Core: e6500, Version: 2.0, (0x80400120) Clock Configuration: CPU0:1600 MHz, CPU1:1600 MHz, CPU2:1600 MHz, CPU3:1600 MHz, DSP CPU0:1200 MHz, DSP CPU1:1200 MHz, DSP CPU2:1200 MHz, DSP CPU3:1200 MHz, DSP CPU4:1200 MHz, DSP CPU5:1200 MHz, CCB:666.667 MHz, DDR:933.333 MHz (1866.667 MT/s data rate) (Asynchronous), IFC:166.667 MHz CPRI:600 MHz MAPLE:600 MHz, MAPLE-ULB:800 MHz, MAPLE-eTVPE:1000 MHz FMAN1: 666.667 MHz QMAN: 333.333 MHz Top level changes include: (1) Top level CONFIG to identify HETEROGENUOUS clusters (2) CONFIGS for SC3900/DSP components (3) Global structures like "cpu_type" and "MPC85xx_SYS_INFO" updated for dsp cores and other components (3) APIs to get DSP num cores and their Mask like: cpu_dsp_mask, cpu_num_dspcores etc same as that of PowerPC (5) Code to fetch and print SC cores and other heterogenous device's frequencies (6) README added for the same Signed-off-by: Shaveta Leekha Reviewed-by: York Sun

powerpc: Add linkage.h file

2015-02-12T17:35:32Z

This permits us to use linux/linkage.h on PowerPC machines. Signed-off-by: Simon Glass

ppc: amcc: Omit unneeded ns16550 CONFIG if using driver model

2015-02-12T17:35:31Z

This comes from the device tree or a call to get_uart_clock(). Signed-off-by: Simon Glass

powerpc: ppc4xx: Add a gpio.h header file

2015-02-12T17:35:31Z

This is required at present for device tree control. The ppc4xx does support GPIOs but does not seem to have a proper driver. So this file is empty. Signed-off-by: Simon Glass

crypto/fsl: Add fixup for crypto node

2015-01-24T04:29:14Z

Era property is added in the crypto node in device tree. Move the code to do so from arch/powerpc/mpc8xxx/fdt.c to drivers/sec/sec.c so that it can be used across arm and powerpc platforms having crypto node. Signed-off-by: Ruchika Gupta [York Sun: Fix commit message indentation] Reviewed-by: York Sun

arch/powerpc: Add SGMII support for the L2 Switch ports

2015-01-16T17:32:26Z

Some Freescale SoCs like T1020 and T1040 have an integrated L2 Switch. The L2 Switch ports may be connected to Ethernet PHYs over SGMII and QSGMII. Signed-off-by: Codrin Ciubotariu Reviewed-by: York Sun

arch/powerpc: Fix mapping of Freescale SerDes protocols

2015-01-16T17:32:20Z

The number of supported serdes protocols on Freescale SoCs has increased over time. Until now, an u64 variable have been initialized on boot with the configured protocols. However, since this number has increased (enum srds_prtcl has more than 64 values), 64 bits are no longer sufficient to hold track of all the configured protocols. This patch replaces the u64 map values with static arrays. To keep track of the number of serdes protocols, the SERDES_PRCTL_COUNT vale has been added at the end of enum srds_prtcl. This value must always be the last one. Signed-off-by: Codrin Ciubotariu Reviewed-by: York Sun