u-boot.git/arch/powerpc/include, branch v2011.03 Unnamed repository; edit this file 'description' to name the repository. powerpc/85xx: Handle PCIe initialization requires for P1021 class SoCs 2011-03-29T12:41:37+00:00 Prabhakar Kushwaha prabhakar@freescale.com 2011-02-01T15:55:58+00:00 b03a466d6ceb9dbfd1a1638f355e9c8b4833259f The P1011, P1012, P1015, P1016, P1020, P1021, P1024, & P1025 SoCs require that we initialize the SERDES registers if the lanes are configured for PCIe. Additionally these devices PCIe controller do not support ASPM and we have to explicitly disable it. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> 
The P1011, P1012, P1015, P1016, P1020, P1021, P1024, & P1025 SoCs require
that we initialize the SERDES registers if the lanes are configured for
PCIe.  Additionally these devices PCIe controller do not support ASPM
and we have to explicitly disable it.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
powerpc/85xx: Enable various errata on P1022/P1013 SoCs 2011-03-28T14:04:26+00:00 Jiang Yutang b14898@freescale.com 2011-01-30T23:06:20+00:00 2d7534a344412409d03e4a341614e4320c48879b Enable workaround for errata ELBC A001, ESDHC 111 & SATA A001 on P1022/P1013 SoCs. Also updated P1022DS config to properly enable CONFIG_FSL_SATA_V2. Signed-off-by: Jiang Yutang <b14898@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> 
Enable workaround for errata ELBC A001, ESDHC 111 & SATA A001 on
P1022/P1013 SoCs.

Also updated P1022DS config to properly enable CONFIG_FSL_SATA_V2.

Signed-off-by: Jiang Yutang <b14898@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
powerpc/mpc8xxx: fix recognition of DIMMs with ECC and Address Parity 2011-03-24T14:20:49+00:00 York Sun yorksun@freescale.com 2011-03-17T18:18:10+00:00 08b3f7599f7bdf7e96cf46ecb9eecffc92b323d2 To recognize DIMMs with ECC capability by testing ECC bit only. Not to be confused by Address Parity bit. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> 
To recognize DIMMs with ECC capability by testing ECC bit only. Not to be
confused by Address Parity bit.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx 2011-02-09T19:50:26+00:00 Wolfgang Denk wd@denx.de 2011-02-09T19:50:26+00:00 fced09ae386d1aa7fcfdf9111c99da4be56e5b43 






ppc4xx: Add DLVision-10G board support
2011-02-07T10:13:16+00:00

Dirk Eibach
eibach@gdsys.de

2011-01-21T08:31:21+00:00

2da0fc0d0fcdd991220cc120e5bc6d44991a5987

Board support for the Guntermann & Drunck DLVision-10G.
Adds support for multiple FPGAs per board for gdsys 405ep
architecture.
Adds support for dual link osd hardware for gdsys 405ep.

Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Stefan Roese <sr@denx.de>





Board support for the Guntermann & Drunck DLVision-10G.
Adds support for multiple FPGAs per board for gdsys 405ep
architecture.
Adds support for dual link osd hardware for gdsys 405ep.

Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Stefan Roese <sr@denx.de>







powerpc/mpc85xx: implement workaround for errata DDR111 and DDR134
2011-02-03T08:46:13+00:00

York Sun
yorksun@freescale.com

2011-01-26T06:05:49+00:00

91671913f7db59dd876e86433d8f3462dbf66588

Workaround for the following errata:
DDR111 - MCKE signal may not function correctly at assertion of HRESET
DDR134 - The automatic CAS-to-Preamble feature of the DDR controller can
         calibrate to incorrect values

These two workarounds must be implemented together because they touch
common registers.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>





Workaround for the following errata:
DDR111 - MCKE signal may not function correctly at assertion of HRESET
DDR134 - The automatic CAS-to-Preamble feature of the DDR controller can
         calibrate to incorrect values

These two workarounds must be implemented together because they touch
common registers.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>







powerpc/85xx: Rename MPC8572 DDR erratum to DDR115
2011-02-03T08:46:13+00:00

York Sun
yorksun@freescale.com

2011-01-26T05:51:27+00:00

eb0aff77c83f70a01dfe47d72b08467c157f7a8b

Use unique erratum number instead of platform number.
Enable command that reports errata on MPC8572DS.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>





Use unique erratum number instead of platform number.
Enable command that reports errata on MPC8572DS.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>







fsl_esdhc: Add the workaround for erratum ESDHC-A001 (enable on P2020)
2011-02-03T08:46:12+00:00

Kumar Gala
galak@kernel.crashing.org

2011-01-29T21:36:10+00:00

5103a03a0be2fd1a5270046d9f2bc77916e33a56

Data timeout counter (SYSCTL[DTOCV]) is not reliable for values of 4, 8,
and 12. Program one more than the desired value: 4 -> 5, 8 -> 9, 12 -> 13.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>





Data timeout counter (SYSCTL[DTOCV]) is not reliable for values of 4, 8,
and 12. Program one more than the desired value: 4 -> 5, 8 -> 9, 12 -> 13.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>







powerpc/85xx: Enable ESDHC111 Erratum on P2010/P2020 SoCs
2011-02-03T08:46:12+00:00

Kumar Gala
galak@kernel.crashing.org

2011-01-26T07:43:15+00:00

6e7f0bc0ce33adbd028f4e34b7e9d3bf46e0f95b

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>





Signed-off-by: Kumar Gala <galak@kernel.crashing.org>







Minor Coding Style Cleanup.
2011-02-02T21:36:10+00:00

Wolfgang Denk
wd@denx.de

2011-02-02T21:36:10+00:00

d1a24f061849ebe4f288d95e8ceb8380f762d323

Signed-off-by: Wolfgang Denk <wd@denx.de>





Signed-off-by: Wolfgang Denk <wd@denx.de>