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<title>u-boot.git/arch/powerpc/include, branch v2011.03-rc2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/powerpc/include?h=v2011.03-rc2</id>
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<updated>2011-03-24T14:20:49Z</updated>
<entry>
<title>powerpc/mpc8xxx: fix recognition of DIMMs with ECC and Address Parity</title>
<updated>2011-03-24T14:20:49Z</updated>
<author>
<name>York Sun</name>
<email>yorksun@freescale.com</email>
</author>
<published>2011-03-17T18:18:10Z</published>
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<id>urn:sha1:08b3f7599f7bdf7e96cf46ecb9eecffc92b323d2</id>
<content type='text'>
To recognize DIMMs with ECC capability by testing ECC bit only. Not to be
confused by Address Parity bit.

Signed-off-by: York Sun &lt;yorksun@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</content>
</entry>
<entry>
<title>Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx</title>
<updated>2011-02-09T19:50:26Z</updated>
<author>
<name>Wolfgang Denk</name>
<email>wd@denx.de</email>
</author>
<published>2011-02-09T19:50:26Z</published>
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<id>urn:sha1:fced09ae386d1aa7fcfdf9111c99da4be56e5b43</id>
<content type='text'>
</content>
</entry>
<entry>
<title>ppc4xx: Add DLVision-10G board support</title>
<updated>2011-02-07T10:13:16Z</updated>
<author>
<name>Dirk Eibach</name>
<email>eibach@gdsys.de</email>
</author>
<published>2011-01-21T08:31:21Z</published>
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<id>urn:sha1:2da0fc0d0fcdd991220cc120e5bc6d44991a5987</id>
<content type='text'>
Board support for the Guntermann &amp; Drunck DLVision-10G.
Adds support for multiple FPGAs per board for gdsys 405ep
architecture.
Adds support for dual link osd hardware for gdsys 405ep.

Signed-off-by: Dirk Eibach &lt;eibach@gdsys.de&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>powerpc/mpc85xx: implement workaround for errata DDR111 and DDR134</title>
<updated>2011-02-03T08:46:13Z</updated>
<author>
<name>York Sun</name>
<email>yorksun@freescale.com</email>
</author>
<published>2011-01-26T06:05:49Z</published>
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<id>urn:sha1:91671913f7db59dd876e86433d8f3462dbf66588</id>
<content type='text'>
Workaround for the following errata:
DDR111 - MCKE signal may not function correctly at assertion of HRESET
DDR134 - The automatic CAS-to-Preamble feature of the DDR controller can
         calibrate to incorrect values

These two workarounds must be implemented together because they touch
common registers.

Signed-off-by: York Sun &lt;yorksun@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</content>
</entry>
<entry>
<title>powerpc/85xx: Rename MPC8572 DDR erratum to DDR115</title>
<updated>2011-02-03T08:46:13Z</updated>
<author>
<name>York Sun</name>
<email>yorksun@freescale.com</email>
</author>
<published>2011-01-26T05:51:27Z</published>
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<id>urn:sha1:eb0aff77c83f70a01dfe47d72b08467c157f7a8b</id>
<content type='text'>
Use unique erratum number instead of platform number.
Enable command that reports errata on MPC8572DS.

Signed-off-by: York Sun &lt;yorksun@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</content>
</entry>
<entry>
<title>fsl_esdhc: Add the workaround for erratum ESDHC-A001 (enable on P2020)</title>
<updated>2011-02-03T08:46:12Z</updated>
<author>
<name>Kumar Gala</name>
<email>galak@kernel.crashing.org</email>
</author>
<published>2011-01-29T21:36:10Z</published>
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<id>urn:sha1:5103a03a0be2fd1a5270046d9f2bc77916e33a56</id>
<content type='text'>
Data timeout counter (SYSCTL[DTOCV]) is not reliable for values of 4, 8,
and 12. Program one more than the desired value: 4 -&gt; 5, 8 -&gt; 9, 12 -&gt; 13.

Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</content>
</entry>
<entry>
<title>powerpc/85xx: Enable ESDHC111 Erratum on P2010/P2020 SoCs</title>
<updated>2011-02-03T08:46:12Z</updated>
<author>
<name>Kumar Gala</name>
<email>galak@kernel.crashing.org</email>
</author>
<published>2011-01-26T07:43:15Z</published>
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<id>urn:sha1:6e7f0bc0ce33adbd028f4e34b7e9d3bf46e0f95b</id>
<content type='text'>
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</content>
</entry>
<entry>
<title>Minor Coding Style Cleanup.</title>
<updated>2011-02-02T21:36:10Z</updated>
<author>
<name>Wolfgang Denk</name>
<email>wd@denx.de</email>
</author>
<published>2011-02-02T21:36:10Z</published>
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<id>urn:sha1:d1a24f061849ebe4f288d95e8ceb8380f762d323</id>
<content type='text'>
Signed-off-by: Wolfgang Denk &lt;wd@denx.de&gt;
</content>
</entry>
<entry>
<title>corenet_ds: Extend board specific parameters</title>
<updated>2011-01-20T04:58:24Z</updated>
<author>
<name>York Sun</name>
<email>yorksun@freescale.com</email>
</author>
<published>2011-01-10T12:03:02Z</published>
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<id>urn:sha1:6b06d7dc071a41e7c9d34447a18acdf53c6bdc4f</id>
<content type='text'>
Extend board specific parameters to include cpo, write leveling override
Extend write leveling sample to 0xf
Adding rcw overrid for quad-rank RDIMMs

Signed-off-by: York Sun &lt;yorksun@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</content>
</entry>
<entry>
<title>mpc85xx: Implement workaround for erratum DDR-A003</title>
<updated>2011-01-20T04:58:24Z</updated>
<author>
<name>York Sun</name>
<email>yorksun@freescale.com</email>
</author>
<published>2011-01-10T12:03:01Z</published>
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<id>urn:sha1:fa8d23c0ee5c66d5cda902ac6ea5b1dfc68d9712</id>
<content type='text'>
Erratum DDR-A003 requires workaround to correctly set RCW10 for registered DIMM.
Also adding polling after enabling DDR controller to ensure completion.

Signed-off-by: York Sun &lt;yorksun@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</content>
</entry>
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