u-boot.git/arch/powerpc/include, branch v2012.04

Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

2012-01-13T19:38:49+00:00

* 'master' of git://git.denx.de/u-boot-mpc85xx:
  fsl_lbc: add printout of LCRR and LBCR to local bus regs
  sbc8548: Fix up local bus init to be frequency aware
  sbc8548: enable support for hardware SPD errata workaround
  sbc8548: relocate fixed ddr init code to ddr.c file
  sbc8548: Make enabling SPD RAM configuration work
  sbc8548: Fix LBC SDRAM initialization settings
  sbc8548: enable ability to boot from alternate flash
  sbc8548: relocate 64MB user flash to sane boundary
  Revert "SBC8548: fix address mask to allow 64M flash"
  MPC85xxCDS: Fix missing LCRR_DBYP bits for 66-133MHz LBC
  eXMeritus HWW-1U-1A: Add support for the AT24C128N I2C EEPROM
  eXMeritus HWW-1U-1A: Minor environment variable tweaks

fsl_lbc: add printout of LCRR and LBCR to local bus regs

2012-01-13T18:56:06+00:00

It can be handy to have these in the output when trying to
debug odd behaviour.

Signed-off-by: Paul Gortmaker 
Signed-off-by: Kumar Gala

mpc83xx: Add a GPIO driver for the MPC83XX family

2012-01-10T02:10:33+00:00

Signed-off-by: Joe Hershberger 
Cc: Joe Hershberger 
Signed-off-by: Kim Phillips

mpc85xx: support for Freescale COM Express P2020

2011-11-29T15:07:51+00:00

This adds support for the Freescale COM Express P2020 board. This board
is similar to the P1_P2_RDB, but has some extra (as well as missing)
peripherals.

Unlike all other mpc85xx boards, it uses a watchdog timeout to reset.
Using the HRESET_REQ register does not work.

This board has no NOR flash, and can only be booted via SD or SPI. This
procedure is documented in Freescale Document Number AN3659 "Booting
from On-Chip ROM (eSDHC or eSPI)." Some alternative documentation is
provided in Freescale Document Number P2020RM "P2020 QorIQ Integrated
Processor Reference Manual" (section 4.5).

Signed-off-by: Ira W. Snyder 
Signed-off-by: Kumar Gala

powerpc/85xx: CONFIG_FSL_SATA_V2 should be defined in config_mpc85xx.h

2011-11-29T14:48:06+00:00

Macro CONFIG_FSL_SATA_V2 is defined if the SOC has a V2 Freescale SATA
controller, so it should be defined in config_mpc85xx.h instead of the various
board header files.  So now CONFIG_FSL_SATA_V2 is always defined on the P1013,
P1022, P2041, P3041, P5010, and P5020.  It was already defined for the
P1010 and P1014.

Signed-off-by: Timur Tabi 
Signed-off-by: Kumar Gala

powerpc/85xx: Add workaround for erratum A-003474

2011-11-29T14:48:06+00:00

Erratum A-003474: Internal DDR calibration circuit is not supported

Impact:
Experience shows no significant benefit to device operation with
auto-calibration enabled versus it disabled. To ensure consistent timing
results, Freescale recommends this feature be disabled in future customer
products. There should be no impact to parts that are already operating
in the field.

Workaround:
Prior to setting DDR_SDRAM_CFG[MEM_EN]=1, do the following:
1. Write a value of 0x0000_0015 to the register at offset
	CCSRBAR + DDR OFFSET + 0xf30
2. Write a value of 0x2400_0000 to the register at offset
	CCSRBAR + DDR OFFSET + 0xf54

Signed-off-by: York Sun 
Signed-off-by: Kumar Gala

powerpc/85xx: Add workaround for erratum CPU-A003999

2011-11-29T14:48:05+00:00

Erratum A-003999: Running Floating Point instructions requires special
initialization.

Impact:
Floating point arithmetic operations may result in an incorrect value.

Workaround:
Perform a read modify write to set bit 7 to a 1 in SPR 977 before
executing any floating point arithmetic operation. This bit can be set
when setting MSR[FP], and can be cleared when clearing MSR[FP].
Alternatively, the bit can be set once at boot time, and never cleared.
There will be no performance degradation due to setting this bit.

Signed-off-by: Kumar Gala

powerpc/85xx: Add support for Book-E MMU Arch v2.0

2011-11-08T14:36:51+00:00

A few of the config registers changed definition between MMU v1.0 and
MMUv2.0.  The new e6500 core from Freescale implements v2.0 of the
architecture.

Specifically, how we determine the size of TLB entries we support in the
variable size (or TLBCAM/TLB1) array is specified in a new register
(TLBnPS - TLB n Page size) instead of via TLBnCFG.

Signed-off-by: Kumar Gala

powerpc/85xx: fix definition of MAS register macros

2011-11-08T14:30:57+00:00

Some of the MAS register macros do not protect the parameter with
parentheses, which could cause wrong values if the parameter includes
operators.

Also fix the definition of TSIZE_TO_BYTES() so that it actually uses
the parameter.  This hasn't caused any problems to date because the
parameter was always been 'tsize'.

Signed-off-by: Timur Tabi 
Signed-off-by: Kumar Gala

powerpc/mpc8548: Add workaround for erratum NMG_eTSEC129

2011-11-08T14:30:32+00:00

Erratum NMG_eTSEC129 (eTSEC86 in MPC8548 document) applies to some early
verion silicons. This workaround detects if the eTSEC Rx logic is properly
initialized, and reinitialize the eTSEC Rx logic.

Signed-off-by: Gong Chen 
Signed-off-by: Zhao Chenhui 
Signed-off-by: Kumar Gala