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<title>u-boot.git/arch/powerpc/include, branch v2013.07</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
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<updated>2013-06-20T22:08:49Z</updated>
<entry>
<title>powerpc/mpc85xx: work around erratum A-006593</title>
<updated>2013-06-20T22:08:49Z</updated>
<author>
<name>Scott Wood</name>
<email>scottwood@freescale.com</email>
</author>
<published>2013-05-15T22:50:13Z</published>
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<id>urn:sha1:8212519254bc3ea94d959f56f10061849aa07b26</id>
<content type='text'>
Erratum A-006593 is "Atomic store may report failure but still allow
the store data to be visible".

The workaround is: "Set CoreNet Platform Cache register CPCHDBCR0 bit
21 to 1'b1.  This may have a small impact on synthetic write bandwidth
benchmarks but should have a negligible impact on real code."

Signed-off-by: Scott Wood &lt;scottwood@freescale.com&gt;
Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
</content>
</entry>
<entry>
<title>fsl_ifc: add support for different IFC bank count</title>
<updated>2013-06-20T22:08:49Z</updated>
<author>
<name>Mingkai Hu</name>
<email>Mingkai.hu@freescale.com</email>
</author>
<published>2013-05-16T02:18:13Z</published>
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<id>urn:sha1:362ee04b797d02117e48312010974d69c325be60</id>
<content type='text'>
Calculate reserved fields according to IFC bank count

1. Move csor_ext register behind csor register and fix res offset
2. Move ifc bank count to config_mpc85xx.h to support 8 bank count
3. Guard fsl_ifc.h with CONFIG_FSL_IFC macro to eliminate the compile
   error on some devices that does not have IFC controller.

Signed-off-by: Mingkai Hu &lt;Mingkai.hu@freescale.com&gt;
Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
</content>
</entry>
<entry>
<title>powerpc/t4qds: Slave module for boot from SRIO and PCIE</title>
<updated>2013-06-20T22:08:49Z</updated>
<author>
<name>Liu Gang</name>
<email>Gang.Liu@freescale.com</email>
</author>
<published>2013-05-07T08:30:50Z</published>
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<id>urn:sha1:69fdf900105d9f730b526c760c082d1f6641a489</id>
<content type='text'>
When a T4 board boots from SRIO or PCIE, it needs to finish these processes:
	1. Set all the cores in holdoff status.
	2. Set the boot location to one PCIE or SRIO interface by RCW.
	3. Set a specific TLB entry for the boot process.
	4. Set a LAW entry with the TargetID of one PCIE or SRIO for the boot.
	5. Set a specific TLB entry in order to fetch ucode and ENV from
	   master.
	6. Set a LAW entry with the TargetID one of the PCIE ports for
	   ucode and ENV.
	7. Slave's u-boot image should be generated specifically by
	   make xxxx_SRIO_PCIE_BOOT_config.
	   This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.

For more information about the feature of Boot from SRIO/PCIE, please
refer to the document doc/README.srio-pcie-boot-corenet.

Signed-off-by: Liu Gang &lt;Gang.Liu@freescale.com&gt;
Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
</content>
</entry>
<entry>
<title>powerpc/b4860qds: Slave module for boot from SRIO and PCIE</title>
<updated>2013-06-20T22:08:48Z</updated>
<author>
<name>Liu Gang</name>
<email>Gang.Liu@freescale.com</email>
</author>
<published>2013-05-07T08:30:48Z</published>
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<id>urn:sha1:5870fe44b2a871c5e70c9facd6692b7c14d1842b</id>
<content type='text'>
When a b4860qds board boots from SRIO or PCIE, it needs to finish these
processes:
	1. Set all the cores in holdoff status.
	2. Set the boot location to one PCIE or SRIO interface by RCW.
	3. Set a specific TLB entry for the boot process.
	4. Set a LAW entry with the TargetID of one PCIE or SRIO for the boot.
	5. Set a specific TLB entry in order to fetch ucode and ENV from
	   master.
	6. Set a LAW entry with the TargetID one of the PCIE ports for
	   ucode and ENV.
	7. Slave's u-boot image should be generated specifically by
	   make xxxx_SRIO_PCIE_BOOT_config.
	   This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.

For more information about the feature of Boot from SRIO/PCIE, please
refer to the document doc/README.srio-pcie-boot-corenet.

Signed-off-by: Liu Gang &lt;Gang.Liu@freescale.com&gt;
Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
</content>
</entry>
<entry>
<title>powerpc/boot: Change the macro of Boot from SRIO and PCIE master module</title>
<updated>2013-06-20T22:08:48Z</updated>
<author>
<name>Liu Gang</name>
<email>Gang.Liu@freescale.com</email>
</author>
<published>2013-05-07T08:30:46Z</published>
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<id>urn:sha1:c8b281524bf98ee5a52db7da71bccdea002df3f5</id>
<content type='text'>
Currently, the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" can enable
the master module of Boot from SRIO and PCIE on a platform. But this
is not a silicon feature, it's just a specific booting mode based on
the SRIO and PCIE interfaces. So it's inappropriate to put the macro
into the file arch/powerpc/include/asm/config_mpc85xx.h.

Change the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" to
"CONFIG_SRIO_PCIE_BOOT_MASTER", remove them from
arch/powerpc/include/asm/config_mpc85xx.h file, and add those macros
in configuration header file of each board which can support the
master module of Boot from SRIO and PCIE.

Signed-off-by: Liu Gang &lt;Gang.Liu@freescale.com&gt;
Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
</content>
</entry>
<entry>
<title>85xx: Change case of MPC85XX_PORBMSR_ROMLOC_SHIFT</title>
<updated>2013-06-20T21:09:09Z</updated>
<author>
<name>Andy Fleming</name>
<email>afleming@freescale.com</email>
</author>
<published>2013-06-20T19:54:33Z</published>
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<id>urn:sha1:8bd00c9494a19ef4ea2a0a9aa695ff111a380850</id>
<content type='text'>
All the other constants use lowercase 'x' in "MPC85xx", so we
duplicate that here.

Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
</content>
</entry>
<entry>
<title>powerpc/BSC9132: Add IFC bank count</title>
<updated>2013-06-20T21:09:09Z</updated>
<author>
<name>York Sun</name>
<email>yorksun@freescale.com</email>
</author>
<published>2013-04-19T02:31:01Z</published>
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<id>urn:sha1:061ffedaafb0a010e19ea386e3f428a4b6419c30</id>
<content type='text'>
BSC9132 has 3 IFC banks.

Signed-off-by: York Sun &lt;yorksun@freescale.com&gt;
Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
</content>
</entry>
<entry>
<title>board/bsc9131rdb: Add DSP side tlb and laws</title>
<updated>2013-06-20T21:09:08Z</updated>
<author>
<name>Priyanka Jain</name>
<email>Priyanka.Jain@freescale.com</email>
</author>
<published>2013-04-04T04:01:54Z</published>
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<id>urn:sha1:765b0bdb899d614d0455f19548901b79f2baa66c</id>
<content type='text'>
BSC9131RDB is a Freescale Reference Design Board for
BSC9131 SoC which is a integrated device that contains
one powerpc e500v2 core and one DSP starcore.

To support DSP starcore
-Creating LAW and TLB for DSP-CCSR space.
-Creating LAW for DSP-core subsystem M2 memory

Signed-off-by: Priyanka Jain &lt;Priyanka.Jain@freescale.com&gt;
Signed-off-by: Poonam Aggrwal &lt;poonam.aggrwal@freescale.com&gt;
Signed-off-by: Prabhakar Kushwaha &lt;prabhakar@freescale.com&gt;
Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
</content>
</entry>
<entry>
<title>powerpc: fix 8xx and 82xx type-punning warnings with GCC 4.7</title>
<updated>2013-06-11T20:01:45Z</updated>
<author>
<name>Scott Wood</name>
<email>scottwood@freescale.com</email>
</author>
<published>2013-05-18T01:01:54Z</published>
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<id>urn:sha1:a166fbca20e40937bf37cc18c389f68e995c1821</id>
<content type='text'>
C99's strict aliasing rules are insane to use in low-level code such as a
bootloader, but as Wolfgang has rejected -fno-strict-aliasing in the
past, add a union so that 16-bit accesses can be performed.

Compile-tested only.

Signed-off-by: Scott Wood &lt;scottwood@freescale.com&gt;
Acked-by: Wolfgang Denk &lt;wd@denx.de&gt;
</content>
</entry>
<entry>
<title>Merge branch 'u-boot/master' into 'u-boot-arm/master'</title>
<updated>2013-05-30T12:45:06Z</updated>
<author>
<name>Albert ARIBAUD</name>
<email>albert.u.boot@aribaud.net</email>
</author>
<published>2013-05-30T12:45:06Z</published>
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<id>urn:sha1:a19b0dd62d7b8efc658fa1aa685ff5665878f3ee</id>
<content type='text'>
Conflicts:
	common/cmd_fpga.c
	drivers/usb/host/ohci-at91.c
</content>
</entry>
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