u-boot.git/arch/powerpc/include, branch v2014.07

powerpc/mpc85xx: Add workaround to enable TDM on T1040

2014-06-05T20:45:07Z

This is a workaround for 32 bit hardware limitation of TDM. T1040 has 36 bit physical addressing, TDM DMAC register are 32 bit wide but need to store address of CCSR space which lies beyond 32 bit address range. This workaround creats a LAW to enable access of TDM DMA to CCSR by mapping CCSR to overlap with DDR. A hole of 16M is created in memory using device tree. This workaround law is set only if "tdm" is defined in hwconfig. Also disable POST tests and add LIODN for TDM Signed-off-by: Sandeep Singh Reviewed-by: York Sun

powerpc/serdes: Add the workaround for erratum A-007186

2014-06-05T20:45:07Z

SerDes PLL is calibrated at reset. When the junction temperature delta from the time the PLL is calibrated exceeds +56C/-66C, jitter may increase and can cause PLL to unlock. This workaround overwrite the SerDes registers with new values, to calibrate SerDes registers. These values are known to work fine for all temperature ranges. This workaround is valid for B4, T4 and T2 platforms, so added in their config. Signed-off-by: Shaveta Leekha Signed-off-by: Poonam Aggrwal [York Sun: replaced typedef ccsr_sfp_regs_t with struct ccsr_sfp_regs] Reviewed-by: York Sun

powerpc/mpc85xx: Add workaround for DDR erratum A004508

2014-06-05T20:45:07Z

When the DDR controller is initialized below a junction temperature of 0°C and then operated above a junction temperature of 65°C, the DDR controller may cause receive data errors, resulting ECC errors and/or corrupted data. This erratum applies to the following SoCs and their variants: MPC8536, MPC8569, MPC8572, P1010, P1020, P1021, P1022, P1023, P2020. Signed-off-by: York Sun

powerpc: hiddendragon: remove orphan board

2014-05-30T18:03:24Z

This board has been orphan for a while. (Emails to its maintainer have been bouncing.) Because MPC82xx family is old enough, nobody would pick up the maintainership on it. Signed-off-by: Masahiro Yamada Cc: Wolfgang Denx

mpc85xx/p1020:Define number of USB controllers used on P1020RDB-PD platform

2014-05-16T21:24:27Z

P1020 SoC which has two USB controllers, but only first one is used on this platform. Signed-off-by: Ramneek Mehresh Reviewed-by: York Sun

powerpc/mpc85xx: Added B4460 support

2014-05-16T21:24:26Z

B4460 differs from B4860 only in number of CPU cores, hence used existing support for B4860. B4460 has 2 PPC cores whereas B4860 has 4 PPC cores. Signed-off-by: Shaveta Leekha Signed-off-by: Sandeep Singh Signed-off-by: Poonam Aggrwal Reviewed-by: York Sun

fsl/pci: Add workaround for erratum A-005434

2014-05-16T21:24:26Z

By default, all PEX inbound windows PEX_PEXIWARn[TRGT] are mapped to 0xF, which is local memory. But for BSC9132, 0xF is CCSR, 0x0 is local memory. Signed-off-by: Minghuan Lian Signed-off-by: Chunhe Lan Reviewed-by: York Sun

powerpc/85xx: add T4080 SoC support

2014-05-13T15:26:54Z

The T4080 SoC is a low-power version of the T4160. T4080 combines 4 dual-threaded Power Architecture e6500 cores with single cluster and two memory complexes. Signed-off-by: Shengzhou Liu

powerpc/t208x: enable errata A006261, A006593, A006379

2014-05-13T15:26:54Z

Enable errata A006261, A006593, A006379 for T208x. Additionally enable CONFIG_CMD_ERRATA for T2080RDB. Signed-off-by: Shengzhou Liu

powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T2080RDB

2014-05-13T15:26:54Z

Secure Boot Target is added for T2080RDB Changes: For Secure boot, CPC is configured as SRAM and used as house keeping area which needs to be disabled. So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T2080RDB. Signed-off-by: Aneesh Bansal