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<title>u-boot.git/arch/powerpc/include, branch v2015.10</title>
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<updated>2015-10-11T21:12:09Z</updated>
<entry>
<title>Revert "powerpc: ppc4xx: remove lwmon5 support"</title>
<updated>2015-10-11T21:12:09Z</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2015-10-02T06:20:35Z</published>
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<id>urn:sha1:04386f656bbc35abd7718a4bbbba7fcfb4f59aef</id>
<content type='text'>
This reverts commit 8fe11b8901a31d11990488c82bc23612589d57be.

I'll add support to lwmon5 in the next patch and will remove
support for the broken lcd4_lwmon5 as well.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Cc: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
</content>
</entry>
<entry>
<title>powerpc: ppc4xx: remove lwmon5 support</title>
<updated>2015-09-02T15:33:13Z</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.masahiro@socionext.com</email>
</author>
<published>2015-09-02T01:40:24Z</published>
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<id>urn:sha1:8fe11b8901a31d11990488c82bc23612589d57be</id>
<content type='text'>
This has not been converted to Generic Board, so should be removed.
(See doc/README.generic-board for details.)

Remove CONFIG_LWMON5 references.
(Also, remove undefined CONFIG_WD_MAX_RATE while I am here.)

Signed-off-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
Cc: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx</title>
<updated>2015-09-02T15:30:46Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2015-09-02T15:30:46Z</published>
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<id>urn:sha1:9809ccdd4c25a068aa8bef883ab66e61ec5fa18b</id>
<content type='text'>
</content>
</entry>
<entry>
<title>SECURE_BOOT: Disable IE Key feature for RAMBOOT</title>
<updated>2015-09-02T02:38:02Z</updated>
<author>
<name>Aneesh Bansal</name>
<email>aneesh.bansal@freescale.com</email>
</author>
<published>2015-07-31T08:40:03Z</published>
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<id>urn:sha1:2ed948f466b2715a82c25ca25f5839c9bbaea6e3</id>
<content type='text'>
ISBC Key Extension feature is not applicable for RAMBOOT
as there is no way to retrieve the CSF Header and validated
IE Key table from SRAM once CPC has been disabled.
The feature is only applicable in case of NOR SECURE BOOT.
Code Cleanup:
The SECURE_BOOT specific defines have been moved from
arch-ls102xa/config.h to
arm/include/asm/fsl_secure_boot.h

Signed-off-by: Aneesh Bansal &lt;aneesh.bansal@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
<entry>
<title>net/fman: Support both new and legacy FMan Compatibles</title>
<updated>2015-09-02T01:57:15Z</updated>
<author>
<name>Igal Liberman</name>
<email>igal.liberman@freescale.com</email>
</author>
<published>2015-08-18T11:47:05Z</published>
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<id>urn:sha1:97a8d010e029111e5711a45264a726bedbeb24c4</id>
<content type='text'>
Recently  the FMan Port and MAC compatibles were changed.
This patch aligns the FMan Port and MAC compatibles
to the new FMan device tree binding document.
The FMan device tree binding document can be found in the Linux kernel:
./Documentation/devicetree/bindings/powerpc/fsl/fman.txt

This patch doesn't affect legacy compatibles support.

Signed-off-by: Igal Liberman &lt;igal.liberman@freescale.com&gt;
Tested-by: Xing Lei &lt;xing.lei@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
<entry>
<title>Correct License and Copyright information on few files</title>
<updated>2015-08-13T00:47:46Z</updated>
<author>
<name>Ruchika Gupta</name>
<email>ruchika.gupta@freescale.com</email>
</author>
<published>2015-07-27T03:37:39Z</published>
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<id>urn:sha1:057c2200557e187a47f2c10af6c0b2db9bf88df3</id>
<content type='text'>
gpio.h - Added missing copyright in few files.
rsa-mod-exp.h - Corrected copyright in the file.
fsl_sec.h - Added missing license in files
drivers/crypto/fsl/Makefile - Removed the incomplete GPLv2 license and replaced it with GPLv2+ license

Signed-off-by: Ruchika Gupta &lt;ruchika.gupta@freescale.com&gt;
</content>
</entry>
<entry>
<title>powerpc/mpc85xx: SECURE BOOT-Copy Boot Script on RAM</title>
<updated>2015-07-31T15:50:18Z</updated>
<author>
<name>Aneesh Bansal</name>
<email>aneesh.bansal@freescale.com</email>
</author>
<published>2015-06-16T05:06:43Z</published>
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<id>urn:sha1:5050f6f0e56af0e02c3e362d9af2b628d6c8da12</id>
<content type='text'>
For running Chain of Trust when doing Secure Boot from NAND,
the Bootscript header and bootscript must be copied from NAND
to RAM(DDR).
The addresses and commands for the same have been defined.

Signed-off-by: Saksham Jain &lt;saksham@freescale.com&gt;
Signed-off-by: Ruchika Gupta &lt;ruchika.gupta@freescale.com&gt;
Signed-off-by: Aneesh Bansal &lt;aneesh.bansal@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
<entry>
<title>powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041</title>
<updated>2015-07-31T15:50:18Z</updated>
<author>
<name>Aneesh Bansal</name>
<email>aneesh.bansal@freescale.com</email>
</author>
<published>2015-06-16T05:06:00Z</published>
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<id>urn:sha1:467a40dfe35f48d830f01a72617207d03ca85b4d</id>
<content type='text'>
Secure Boot Target is added for NAND for P3041.
For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC.
In case of secure boot, this default address maps to Boot ROM.
The Boot ROM code requires that the bootloader(U-boot) must lie
in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF.

In case of NAND Secure Boot, CONFIG_SYS_RAMBOOT is enabled and CPC is
configured as SRAM. U-Boot binary will be located on SRAM configured
at address 0xBFF00000.
In the U-Boot code, TLB entries are created to map the virtual address
0xFFF00000 to physical address 0xBFF00000 of CPC configured as SRAM.

Signed-off-by: Saksham Jain &lt;saksham@freescale.com&gt;
Signed-off-by: Ruchika Gupta &lt;ruchika.gupta@freescale.com&gt;
Signed-off-by: Aneesh Bansal &lt;aneesh.bansal@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
<entry>
<title>powerpc/mpc85xx: Correct CONFIG_USB_MAX_CONTROLLER_COUNT for p1025</title>
<updated>2015-07-28T21:41:16Z</updated>
<author>
<name>Nikhil Badola</name>
<email>nikhil.badola@freescale.com</email>
</author>
<published>2015-05-21T03:37:53Z</published>
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<id>urn:sha1:1ff10a87c32acf8ec4e8676c4e01dbcc8b255ec3</id>
<content type='text'>
Correct the value CONFIG_USB_MAX_CONTROLLER_COUNT macro to 1
for p1025 as it has one USB controller

Signed-off-by: Nikhil Badola &lt;nikhil.badola@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
<entry>
<title>powerpc/t1024: update fman liodn for mac1</title>
<updated>2015-07-28T21:41:15Z</updated>
<author>
<name>Shengzhou Liu</name>
<email>Shengzhou.Liu@freescale.com</email>
</author>
<published>2015-05-14T08:51:39Z</published>
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<id>urn:sha1:b99b6452bce169df009a1e99b5b5e25b3320cacc</id>
<content type='text'>
MAC1 acts as 1G/10G dual-role MAC on T1024. We introduce
macro SET_FMAN_RX_10G_TYPE2_LIODN for 10G MACs which have
same Port ID and same offset of address with 1G MAC.
Update it to match with the setting of fman in t1024 device
tree, otherwise there is no 'fsl,liodn' in
/proc/device-tree/soc@ffe000000/fman@400000/port@88000/

Signed-off-by: Shengzhou Liu &lt;Shengzhou.Liu@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
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