Unnamed repository; edit this file 'description' to name the repository. http://cgit.235523.xyz/u-boot.git/atom/arch/powerpc/include?h=v2019.01 2018-12-05T20:06:24Z 2018-12-05T20:06:24Z Tom Rini trini@konsulko.com 2018-12-05T20:06:24Z urn:sha1:9450ab2ba8d720bd9f73bccc0af2e2b5a2c2aaf1 - Various MTD fixes from Boris - Zap various unused / legacy paths. - pxa3xx NAND update from Miquel Signed-off-by: Tom Rini <trini@konsulko.com> 2018-11-27T15:36:53Z Jagan Teki jagan@amarulasolutions.com 2018-11-24T09:01:12Z urn:sha1:35f9d9bdd07d5e508272421b215ffaffd867bad8 In legacy CONFIG_HARD_SPI initalizing spi_init code, which was removed during dm conversion cleanup. So remove the dead instances of CONFIG_HARD_SPI, and related code. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> 2018-11-26T13:25:37Z Simon Glass sjg@chromium.org 2018-11-16T01:44:09Z urn:sha1:b0edea3c27af3bf7b959fa190a7fe9d7881153c5 There is some basic informaton that SPL normally wants to pass through to U-Boot, such as the SDRAM size and bank information. Mkae use of the new bloblist structure for this. Add a new 'handoff' blob which is set up in SPL and passed to U-Boot proper. Also adda test for sandbox_spl that checks that this works correctly and a new 'sb' command to show the information passed from SPL. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Simon Glass <sjg@chromium.org> 2018-10-29T20:19:43Z Bin Meng bmeng.cn@gmail.com 2018-10-08T13:55:57Z urn:sha1:db148f2a6938b47cf26c5fd11481e7462a6a793a Per T1040RM (Rev. 1, 08/2015), there are 2 issues with the RCW EC2 settings. - The value of FSL_CORENET_RCWSR13_EC2_FM1_GPIO is wrong and should be 0x04000000 (value of 1 in RCW bit [420:421]) - Value of 2/3 are reserved in RCW bit [420:421], hence there is no macro FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Poonam Aggrwal <poonam.aggrwal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> 2018-10-29T20:13:33Z Bin Meng bmeng.cn@gmail.com 2018-10-08T13:55:56Z urn:sha1:c00d0012f5d6aa3987f5465caf8b6ead5ac919ff Per T1040RM (Rev. 1, 08/2015), the value of FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT is wrong and should be 0x00000080 (bit 440 in the RCW). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Poonam Aggrwal <poonam.aggrwal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> 2018-09-18T14:12:21Z Mario Six mario.six@gdsys.cc 2018-08-06T08:23:46Z urn:sha1:d2166319df17286b2a3e2a1a7ce89f01e4f8bac9 Add a driver to configure the SerDes (Serializer/Deserializer) lanes on the MPC83xx architecture. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc> 2018-09-18T14:12:21Z Mario Six mario.six@gdsys.cc 2018-08-06T08:23:45Z urn:sha1:19fbdca47b3d847824ada3ab2ed575019c88516e Add a CPU driver for the MPC83xx architecture. Signed-off-by: Mario Six <mario.six@gdsys.cc> 2018-09-18T06:01:18Z Mario Six mario.six@gdsys.cc 2018-08-06T08:23:36Z urn:sha1:07d538d2814fa03be243c71879372f4263030b78 Add a clock driver for the MPC83xx architecture. Signed-off-by: Mario Six <mario.six@gdsys.cc> 2018-09-18T06:01:18Z Mario Six mario.six@gdsys.cc 2018-08-06T08:23:31Z urn:sha1:08f5b0b23a62ac7d1b705241f16df1e3a1cb8ae1 Define the read*_*/write*_* macros for the PowerPC platform to be able to use the macros in wait_bit.h. Signed-off-by: Mario Six <mario.six@gdsys.cc> 2018-09-11T00:48:16Z Masahiro Yamada yamada.masahiro@socionext.com 2018-08-06T11:47:39Z urn:sha1:3747bdbb2bb83a3bb2e7bd823856de4f4908f711 All architectures have the same definition for s8/16/32/64 and u8/16/32/64. Factor out the duplicated code into <asm-generic/int-ll64.h>. BTW, Linux unified the kernel space definition into int-ll64.h a few years ago as you see in Linux commit 0c79a8e29b5f ("asm/types.h: Remove include/asm-generic/int-l64.h"). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>